Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2005-09-27
2005-09-27
Rinehart, Mark H. (Department: 2111)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S054000, C709S232000, C370S389000
Reexamination Certificate
active
06950886
ABSTRACT:
A method and apparatus for reordering transactions in a packet-based fabric using I/O Streams. Packet bus transactions may flow upstream from node to node on a non-coherent I/O packet bus. Some peripheral buses place ordering constraints on their bus transactions to prevent deadlock situations. When a packet transaction originating on a peripheral bus with ordering constraints is translated to a packet bus such as the non-coherent I/O packet bus, those same ordering constraints may be mapped over to the packet bus transactions. To efficiently handle the packets and prevent deadlock situations, packets may be handled and reordered on an I/O stream basis. Thus, reordering logic may consider I/O streams independently and therefore only reorder transactions within an I/O stream and not across more than one I/O stream.
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Advanced Micro Devices , Inc.
Cleary Thomas J.
Kivlin B. Noäl
Rinehart Mark H.
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