Method, apparatus, and system to enhance negative voltage...

Details Method, apparatus, and system to enhance negative voltage... Method, apparatus, and system to enhance negative voltage...

2005-09-13

2005-09-13

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Simultaneous operations

C365S185010, C365S185180, C365S185290, C365S189011

Reexamination Certificate

active

06944065

ABSTRACT:
The present invention is in the field of flash memory. More particularly, embodiments of the present invention may provide a negative voltage for erasing when coupled to a memory cell to be erased and provide voltages to read or program when not coupled to a memory cell that is selected to be erased. Embodiments may also provide a high magnitude negative voltage to erase; a low impedance, low voltage current to read or program; and burn little to no current when not coupled to a memory cell that is selected to be erased.

REFERENCES:
patent: 5491656 (1996-02-01), Sawada
patent: 5663907 (1997-09-01), Frayer et al.
patent: 6571307 (2003-05-01), Kuo et al.

Affiliated with

Also associated with

Rating

Method, apparatus, and system to enhance negative voltage... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method, apparatus, and system to enhance negative voltage..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method, apparatus, and system to enhance negative voltage... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3384513