Semiconductor memory device having a power-on reset circuit

Details Semiconductor memory device having a power-on reset circuit Semiconductor memory device having a power-on reset circuit

2005-05-31

2005-05-31

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S189011, C365S189050, C365S189070

Reexamination Certificate

active

06901012

ABSTRACT:
A semiconductor device includes an internal power supply terminal for supplying an internal power supply voltage, an oscillator generating a clock pulse when the internal power supply voltage becomes higher than a first voltage, a charge pump circuit charge pumping upon receiving the clock pulse, a reference voltage generator using the output voltage from the charge pump circuit as a power supply, and a voltage monitor which uses the output voltage from the charge pump circuit as a power supply, has a comparator for comparing a divided voltage of the internal power supply voltage with the reference voltage, and outputs a first signal of a first logic level as the power-on reset signal when the internal power supply voltage is higher than a second voltage. With this arrangement, a power-on reset circuit with little variation in power-on monitoring level can be provided.

REFERENCES:
patent: 5805509 (1998-09-01), Leung et al.
patent: 5912575 (1999-06-01), Takikawa
patent: 5969998 (1999-10-01), Oowaki et al.
patent: 5986935 (1999-11-01), Iyama et al.
patent: 6205079 (2001-03-01), Namekawa
patent: 6487118 (2002-11-01), Iwata et al.
patent: 2001/0017566 (2001-08-01), Nakahara
patent: 02-228064 (1990-09-01), None
patent: 2001-184882 (2001-07-01), None
H. Tanaka et al, “A Precise-On-Chip Voltage Generator for a Gigascale DRAM with a Negative Word-Line Scheme”, IEEE Journal of Solid-State Circuits, vol. 34, No. 8, pp. 1084-1090, Aug. 1999.

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