Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-05-24
2005-05-24
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06898773
ABSTRACT:
Some embodiments of the invention provide a method for identifying topological routes in a multi-layer region of a design layout. The method selects a first net that has several routable elements. For the selected net, it then specifies a first multi-layer topological route that connects the first net's routable elements before selecting another net for routing. The first topological route traverses a plurality of layers. In addition, a topological route is a route that represents a set of diffeomorphic geometric routes.
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Caldwell Andrew
Teig Steven
Cadence Design Systems Inc.
Do Thuan
Stattler Johansen & Adeli LLP
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