Programmable error checking value circuit and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Reexamination Certificate

active

06883132

ABSTRACT:
An arbiter system comprises a plurality of hardware resources, a common resource, and an arbiter. The plurality of hardware resources are divided into groups of hardware resources and are coupled to the common resource and the arbiter. The arbiter controls which of the plurality of hardware resources has priority to access to the common resource. The arbiter includes a group shifting arbiter which shifts priority among the groups of hardware resources and a level shifting arbiter which separately shifts priority among the hardware resources within each of the groups. An error checking value generator system comprises a general purpose DMA controller and an arithmetic circuit. The arithmetic circuit is coupled to receive data from the general purpose DMA controller. The arithmetic circuit generates an error checking value based on the data received from the general purpose DMA controller and based on a polynomial equation. The arithmetic circuit is capable of being programmed with a plurality of different polynomial equations usable to generate error checking values of different types.

REFERENCES:
patent: 4216540 (1980-08-01), McSpadden
patent: 4314335 (1982-02-01), Pezzi
patent: 4325119 (1982-04-01), Grandmaison et al.
patent: 4604748 (1986-08-01), Sato
patent: 4639863 (1987-01-01), Harrison et al.
patent: 4713605 (1987-12-01), Iyer et al.
patent: 4771429 (1988-09-01), Davis et al.
patent: 4780814 (1988-10-01), Hayek
patent: 4819153 (1989-04-01), Graham et al.
patent: 4924380 (1990-05-01), McKinney et al.
patent: 5130990 (1992-07-01), Hsu et al.
patent: 5138620 (1992-08-01), Miyazaki
patent: 5301333 (1994-04-01), Lee
patent: 5327436 (1994-07-01), Miyazaki
patent: 5655151 (1997-08-01), Bowes et al.
patent: 5729702 (1998-03-01), Creedon et al.
patent: 5832278 (1998-11-01), Pham
patent: 5928372 (1999-07-01), Yoshida
patent: 6006303 (1999-12-01), Barnaby et al.
patent: 6023738 (2000-02-01), Priem et al.
patent: 6026443 (2000-02-01), Oskouy et al.
patent: 6088517 (2000-07-01), Wanner et al.
patent: 6092116 (2000-07-01), Earnest et al.
patent: 6092231 (2000-07-01), Sze
patent: 6385751 (2002-05-01), Wolf

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Programmable error checking value circuit and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable error checking value circuit and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable error checking value circuit and method will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3381698

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.