Low power clock distribution scheme

Details Low power clock distribution scheme Low power clock distribution scheme

2005-04-12

2005-04-12

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S041000, C326S047000, C326S101000, C327S141000, C327S144000, C327S145000

Reexamination Certificate

active

06879185

ABSTRACT:
An electronic circuit containing one or more digital synchronous sequential logic blocks at least one of which is either selected or deselected during operation. The electronic circuit includes an improved clock distribution scheme that reduces power consumption, comprising identifying means for determining the select/deselect state of each said deselectable synchronous sequential logic block, coupled to disabling means for disabling the clock input to each deselected synchronous sequential logic block.

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