Method and system for manufacturing DRAMs with reduced...

Details Method and system for manufacturing DRAMs with reduced... Method and system for manufacturing DRAMs with reduced...

2005-09-06

2005-09-06

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S189011, C365S230060

Reexamination Certificate

active

06940773

ABSTRACT:
A method and system for reducing self-refresh current requirements in a includes a DRAM chip that is sectioned into a number of segments. The entire DRAM chip is tested upon manufacture to determine the relative decay rates for each cell in the DRAM. For each segment, the refresh rate for that segment is selected based on the fastest decay rate for a DRAM cell in the segment. The DRAM is configured for refreshing memory cells during a self-refresh at different refresh rates for different segments. The refresh period is controlled for individual segments using techniques, such as programmable logic or fuses, to skip certain self-refresh cycles for those segments capable of operating at lower refresh rates. The refresh period in memory segments with strong memory cells can be reduced, thereby conserving current required to be drawn.

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