Semiconductor memory device with structure of converting...

Details Semiconductor memory device with structure of converting... Semiconductor memory device with structure of converting...

2005-07-05

2005-07-05

Tran, M. (Department: 2818)

Static information storage and retrieval

Read/write circuit

C365S189040

Reexamination Certificate

active

06914828

ABSTRACT:
An amplifier circuit (R/A) conducts the first stage of ordering of whether to output data of four data bus pairs at the first half (first or second) or at the last half (third or fourth) based on the value of a signal EZORG1reflecting the value of the least significant second bit of an externally applied column address. A switch circuit conducts the second stage of ordering to determine which is to be the first and the second of the two data output as the first half and to determine which is to be the third and the fourth of the two data output as the last half based on the value of a signal EZORG0reflecting the value of the least significant bit in the externally applied column address.

REFERENCES:
patent: 6707740 (2004-03-01), Shinozaki
patent: 08-17184 (1996-01-01), None
patent: P2000-163969 (2000-06-01), None

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