Memory device and memory system

Static information storage and retrieval – Read/write circuit – Signals

Reexamination Certificate

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Details

C365S063000, C326S021000, C326S030000, C710S100000

Reexamination Certificate

active

06917546

ABSTRACT:
In a memory device which is used with the memory device connected to a data bus, the memory device includes an active termination circuit for terminating the memory device when the active termination circuit is electrically put into an active state and for unterminating the memory device when the active termination circuit is electrically put into an inactive state. The memory device further includes a control circuit for controlling the active termination circuit to electrically put the active termination circuit into the active state or the inactive state.

REFERENCES:
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patent: 5729152 (1998-03-01), Leung et al.
patent: 6356106 (2002-03-01), Greeff et al.
patent: 6538951 (2003-03-01), Janzen et al.
patent: 2003/0099138 (2003-05-01), Kyung
patent: 2003/0126338 (2003-07-01), Dodd et al.
patent: 06-104725 (1994-04-01), None
patent: 07-074606 (1995-03-01), None
patent: 07-135513 (1995-05-01), None
patent: 07-182078 (1995-07-01), None
patent: 10-020974 (1998-01-01), None
patent: 10-268992 (1998-10-01), None
patent: 11-066842 (1999-03-01), None
patent: 2002-033774 (2002-01-01), None
patent: 2002-082744 (2002-03-01), None
patent: 2002-230963 (2002-08-01), None
Korean Office Action with Translation dated Sep. 21, 2004.
Japanese Office Action, Jun. 16, 2004.

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