Unified exception handling for hierarchical multi-interrupt...

Details Unified exception handling for hierarchical multi-interrupt... Unified exception handling for hierarchical multi-interrupt...

2005-04-12

2005-04-12

Rinehart, Mark H. (Department: 2112)

Electrical computers and digital data processing systems: input/

Interrupt processing

Handling vector

C710S262000

Reexamination Certificate

active

06880030

ABSTRACT:
A unified interrupt handling system and method is provided for an embeddable processor having multiple interrupt types. An instruction is inserted into the first vector address that disables the second interrupt mode. At the second vector address, an other instruction is inserted that branches to a common interrupt dispatcher. The common interrupt dispatcher is provided with an interrupt routine that processes the interrupt, and then re-enables the second interrupt modes. Interrupt requests are then processed by the common interrupt dispatcher without interruption.

REFERENCES:
patent: 20020016880 (2002-02-01), Bhagat
patent: 20020099933 (2002-07-01), Nevill et al.
Disabling Interrupts at Processor Level, Atmel AT91 ARM THUMB Microcontrollers, Application Note, Rev 1156A, 8/98, 3 pp. (http://www.eetasia.com/ARTICLES/2000AUG/2000AUG29_CT_AN7.PDF).*
Application Note 25: Exception handling on the ARM (including thumb-aware processors), ARM DAI 0025E, Advanced RISC Machines Ltd (ARM) Sep. 1996, 36 pp.*
Application Note 31: Using embeddedICE, ARM DAI 0031C Advanced RISC Machines Ltd (ARM) Feb. 1999, 30 pp.*
ARM architecture reference manual, ver B (et seq.), Jul. 26, 1996, pp. 2.1-2.10.

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