Method and apparatus for defining vias

Details Method and apparatus for defining vias Method and apparatus for defining vias

2005-05-24

2005-05-24

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06898772

ABSTRACT:
Some embodiments of the invention provide a method for identifying locations of potential via between two layers of a design layout. The method identifies on one layer a first non-rectangular polygonal region for containing the via, and identifies on the other layer a second non-rectangular polygonal region for containing the via. It then determines whether an intersection of the first and second regions is sufficiently large to contain a via. If the intersection is sufficiently large, the method identifies the intersection of the two regions as a region for containing a via.

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