Multiple chip system including a plurality of non-volatile...

Details Multiple chip system including a plurality of non-volatile... Multiple chip system including a plurality of non-volatile...

2005-05-03

2005-05-03

Auduong, Gene N. (Department: 2818)

Static information storage and retrieval

Format or disposition of elements

C365S052000, C365S191000

Reexamination Certificate

active

06888733

ABSTRACT:
A multiple chip memory system capable of providing state information relating to each chip embedded therein. The multiple chip memory system includes a first chip enabled by a first chip selection signal, and informing of a self state by a first ready/busy signal; and a second chip enabled by a second chip selection signal, and informing of a self state by a second ready/busy signal.

REFERENCES:
patent: 5812814 (1998-09-01), Sukegawa
patent: 5822251 (1998-10-01), Bruce et al.
patent: 6438045 (2002-08-01), King et al.
patent: 6680858 (2004-01-01), Nakamura et al.

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