Register array having timing reference sensing function,...

Details Register array having timing reference sensing function,... Register array having timing reference sensing function,...

2005-03-08

2005-03-08

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

With shift register

C365S203000, C365S189110, C365S207000

Reexamination Certificate

active

06865120

ABSTRACT:
The present invention discloses a ferroelectric random access memory having a multi-bit line structure. The ferroelectric random access memory includes a plurality of cell array blocks for storing cell data, a common data bus unit for transmitting read/write data, and a timing data register array unit for sensing the read data and outputting the write data to the common data bus unit. The timing data register array unit senses the read data by using timing of a sensing voltage of the common data bus unit to reach the sensing threshold voltage. As a result, the ferroelectric random access memory improves a sensing margin in a low voltage and increases a sensing speed.

REFERENCES:
patent: 5563831 (1996-10-01), Ting
patent: 6172925 (2001-01-01), Bloker
patent: 1019980014400 (2000-07-01), None

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