Method for eliminating via blocking in an IC design

Details Method for eliminating via blocking in an IC design Method for eliminating via blocking in an IC design

2005-04-12

2005-04-12

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06880143

ABSTRACT:
An IC design indicating positions of cells within an IC is processed to determine whether conductors residing above the cells block via access to an input/output (I/O) terminal on an upper surface of any of the cells. Each cell spans several contiguous via spaces in a horizontal direction with each via space being sufficiently wide in that direction to contain a via extending upward from any I/O terminal occupying that via space. For each cell having an I/O terminal requiring via access, a separate first data word corresponding to each I/O terminal of that cell is generated. Each bit of the first data word corresponds to a separate one of the via spaces spanned by the cell and indicates whether the I/O terminal corresponding to that first data word occupies that via space. The IC design is also processed to generate a second data word for each cell, wherein each bit of the second data word also corresponds to a separate one of the via spaces spanned by the cell and indicates whether any one of the conductors occupies that via space. The second data word is logically ANDed with each first data word to produce a separate third data word corresponding to each I/O terminal indicating whether the conductors block via access to the I/O terminal.

REFERENCES:
patent: 5315534 (1994-05-01), Schlachet
patent: 5483461 (1996-01-01), Lee et al.
patent: 5487037 (1996-01-01), Lee
patent: 5793643 (1998-08-01), Cai
patent: 6404226 (2002-06-01), Schadt

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