Semiconductor chip package with interconnect structure

Details Semiconductor chip package with interconnect structure Semiconductor chip package with interconnect structure

2005-07-26

2005-07-26

Gurley, Lynne A. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S598000, C438S599000, C438S612000, C438S613000, C438S614000, C438S615000, C438S617000, C438S618000, C438S687000

Reexamination Certificate

active

06921713

ABSTRACT:
An active microelectronic element such as a semiconductor chip or wafer is bonded to an interconnect element having substantially the same coefficient of thermal expansion as the active element using small, rigid bonds, desirably made by a solid-phase bonding technique, which accommodate numerous closely-spaced interconnections. The assembly is provided with terminals movable with respect to the active element and interconnect element. The interconnect element desirably provides low-impedance conductive paths interconnecting active electronic devices within the active element.

REFERENCES:
patent: 4818728 (1989-04-01), Rai et al.
patent: 5148265 (1992-09-01), Khandros et al.
patent: 5148266 (1992-09-01), Khandros et al.
patent: 5281151 (1994-01-01), Arima et al.
patent: 5286680 (1994-02-01), Cain
patent: 5455390 (1995-10-01), DiStefano et al.
patent: 5518964 (1996-05-01), DiStefano et al.
patent: 5640049 (1997-06-01), Rostoker et al.
patent: 5688716 (1997-11-01), DiStefano et al.
patent: 5706174 (1998-01-01), Distefano et al.
patent: 5756395 (1998-05-01), Rostoker et al.
patent: 5763941 (1998-06-01), Fjelstad
patent: 5798286 (1998-08-01), Faraci et al.
patent: 5802699 (1998-09-01), Fjelstad et al.
patent: 5812378 (1998-09-01), Fjelstad et al.
patent: 5976913 (1999-11-01), Distefano
patent: 5989936 (1999-11-01), Smith et al.
patent: 6002168 (1999-12-01), Bellaar et al.
patent: 6218215 (2001-04-01), Distefano et al.
patent: 6492251 (2002-12-01), Haba
patent: 6573609 (2003-06-01), Fjelstad et al.
patent: 2001/0048591 (2001-12-01), Fjelstad et al.
patent: WO-96/02068 (1996-01-01), None
patent: WO-97/11486 (1997-03-01), None
patent: WO-97/11588 (1997-03-01), None
patent: WO-97/40958 (1997-11-01), None
patent: WO-98/44564 (1998-10-01), None
patent: WO-98/445564 (1998-10-01), None

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