Method of patterning lines in semiconductor devices

Details Method of patterning lines in semiconductor devices Method of patterning lines in semiconductor devices

2005-04-05

2005-04-05

Chen, Jack (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S666000, C438S669000, C438S672000, C438S673000

Reexamination Certificate

active

06875689

ABSTRACT:
A new process is provided for the creation of sub-micron conductive lines and patterns. A conductive layer is deposited over the surface of a substrate, a sacrificial layer that differs with the conductive layer in etch characteristics is deposited over the surface of the conductive layer. The sacrificial layer is patterned and etched, creating an opening in the sacrificial layer that aligns with but is larger in cross section than the to be created sub-micron conductive lines and patterns. A spacer layer is deposited over the surface of which a hard mask layer is deposited, filling the opening in the sacrificial layer. The hard mask layer is polished down to the surface of the spacer layer, leaving the hard mask layer in place overlying the spacer layer inside the opening created in the sacrificial layer. Using the hard mask layer as a mask, the spacer layer, the sacrificial layer and the conductive layer are etched, leaving in place the hard mask layer overlying the etched spacer layer, which overlies the etched conductive layer. The etched conductive layer now has a cross section that equals the cross section of the hard mask layer. Removing the hard mask layer and the spacer layer leaves the conductive layer in place, having a cross section that is significantly smaller than the cross section of a conventionally created sub-micron conductive lines and patterns.

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