Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2003-02-14
2004-06-15
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S766000, C438S778000
Reexamination Certificate
active
06750127
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention pertains to fabrication of semiconductor devices, and in particular to fabrication techniques using an amorphous carbon hardmask for etching polysilicon.
2. Related Technology
An emphasis on increased semiconductor device performance has led to investigation of ways to increase device speed. One way of increasing device speed is to reduce the size of individual circuit components and the wiring that connects them. This enables circuit components to operate faster and to be placed closer together, and enables more circuit components to be used in a given device.
One obstacle to reduction of device sizes is the minimum feature size that can be produced through projection lithography, which is related to the wavelength of energy used by the projection lithography system. As a result, supplemental techniques have been developed to produce structures with dimensions that are less than the minimum projection lithography feature size. One such technique involves the trimming of mask structures by isotropic etches prior to patterning of underlying layers.
FIG. 1
shows an example of a structure to which the trimming technique may be applied. In
FIG. 1
, a substrate
10
has formed thereon a silicon oxide gate insulating layer
12
and a polysilicon gate conductive layer
14
that are to be patterned to form a gate line and gate insulator. A hardmask layer
16
such as silicon oxynitride is formed over the polysilicon layer
14
, and a photoresist mask
18
is formed over the hardmask layer
16
. For purposes of this example, it is assumed that the photoresist mask has the minimum width that can be produced by projection lithography. In subsequent processing, the photoresist mask
18
is trimmed through exposure to an isotropic oxygen plasma that consumes part of the photoresist, thus reducing the width of the photoresist mask and structures patterned using the photoresist mask. The hardmask layer
16
is then patterned using the trimmed photoresist mask as an etch mask. The resulting hardmask structure is subjected to another trimming etch to reduce the width of the hardmask structure, and the trimmed hardmask is then used to pattern the underlying polysilicon to form a narrow gate line. Thus the width of the gate line is narrower than the minimum feature size of the projection lithography system used to produce the photoresist mask
18
.
To further exploit the trim technique, it has been proposed to use additional layers in the hardmask structure so that further trimming may be performed at each additional layer. One proposed structure is shown in FIG.
2
. The structure of
FIG. 2
differs from the structure of
FIG. 1
in that it includes a layer of amorphous carbon
20
between the polysilicon layer
14
and the silicon oxynitride layer
16
. During pattern transfer, a hardmask structure formed in the amorphous carbon layer
20
may be trimmed prior to patterning of the underlying polysilicon layer
14
to achieve further reductions in feature size.
The use of an amorphous carbon layer as the bottom layer of a multi-layer hardmask structure as shown in
FIG. 2
is desirable because any amorphous carbon remaining after completion of the polysilicon etch is easily removed by ashing in an isotropic oxygen or hydrogen plasma without damaging the polysilicon or other exposed materials. However, it has proven difficult to achieve accurate pattern transfer with amorphous carbon hardmasks because of the low resistivity of amorphous carbon to the chlorine or HBr chemistry used to etch the polysilicon. This problem is illustrated in
FIGS. 3
a
and
3
b
.
FIG. 3
a
shows a trimmed amorphous carbon hardmask
22
that overlies a polysilicon layer
14
.
FIG. 3
b
shows the structure of
FIG. 3
a
after etching of the polysilicon. It may be seen by comparison of
FIG. 3
b
to
FIG. 3
a
that the polysilicon etch consumes a significant portion of the amorphous carbon hardmask
22
, resulting in reduction of its width during the course of the etch and a corresponding tapering of the resulting gate line
24
. In some instances, the loss of amorphous carbon may result in a gate line that is too thin, causing a pattern deformation that can result in loss of pattern control, loss of critical dimension control, and difficulty in controlling polysilicon line thickness. If the amorphous carbon is consumed completely, a reduction in the height of the gate line will result.
SUMMARY OF THE INVENTION
In view of the aforementioned problems of the background technology, there is a need for additional techniques to improve the pattern transfer accuracy of amorphous carbon hardmasks.
In accordance with a preferred embodiment of the invention, an amorphous carbon layer is implanted with one or more dopants that enhance the etch resistivity of the amorphous carbon to etchants such as chlorine and HBr that are typically used to etch polysilicon. Such a layer may be patterned to form a hardmask for etching polysilicon that provides improved pattern transfer accuracy compared to undoped amorphous carbon.
In accordance with one embodiment of the invention, a polysilicon structure is patterned using a doped amorphous carbon hardmask. Initially a substrate is provided. The substrate has a polysilicon layer formed thereon. An amorphous carbon layer is formed on the polysilicon layer. The amorphous carbon layer is then implanted with a dopant that increases the resistance of the amorphous carbon to etching by chemistry used to etch polysilicon. Examples of such dopants are nitrogen, argon, boron and arsenic. An amorphous carbon hardmask is then formed by patterning the amorphous carbon layer. In a preferred embodiment this is achieved through the use of an overlying hardmask layer that is patterned to form a hardmask for etching the amorphous carbon. However, one or more additional layers may be employed, and photoresists masks and hardmasks may be trimmed before etching of underlying layers. The polysilicon layer is then patterned using the amorphous carbon hardmask as an etch mask. Further processing may then be performed, such as ashing of the amorphous carbon hardmask, etching of a gate insulating layer to form a gate insulator, formation of source and drain diffusions, or formation of source and drain contacts.
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Yamaguchi, A. et al., “Ar Ion implantation into Resist For Etching Resistance Improvement”, Proceedings of SPIE vol. 4345 (2001), pp. 655-664.
Borzenko, V. et al., “The Effect of Ion Implantation On Polymer Mask Resistance To Ion Beam Etching”, Vacuum, 38, 1007 (1988), pp. 1007-1009.
Bell Scott A.
Bonser Douglas J.
Chan Darin
Chang Mark S.
Dakshina-Murthy Srikanteswara
Foley & Lardner LLP
Niebling John F.
Pompey Ron
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