Ternary content addressable memory device

Details Ternary content addressable memory device Ternary content addressable memory device

2002-11-25

2004-06-08

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S168000, C365S189070

Reexamination Certificate

active

06747885

ABSTRACT:

This application claims priority to Korean Patent Application No. 2002-36626, filed on Jun. 28, 2002, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a content addressable memory cell (hereinafter referred to as “CAM cell”) and, more particularly, to a ternary content addressable memory cell (hereinafter referred to as “TCAM cell”) capable of storing three states of information.
2. Discussion of Related Art
A CAM is a memory which is addressed by its own contents. Different from a RAM or ROM wherein an address is used to indicate a specific position in its memory cell array and outputs data stored in the addressed position, a CAM is externally supplied with data, and searches are made within the contents of the CAM for a match with the supplied data, and outputs an address depending on a comparison result. Each cell of a CAM includes comparison logic. A data value input to the CAM is compared with data stored in all the cells simultaneously. The matched result is the address. A CAM is commonly used in applications requiring fast searches for a pattern, a list, image data, etc.
A CAM cell may be classified into a binary CAM cell and a TCAM cell. A typical binary CAM cell is configured with a RAM cell to store one of two states of information, i.e., a logic “1” state and a logic “0” state. The binary CAM cell includes a compare circuit that compares data supplied externally (hereinafter, ‘comparand data’) with data stored in the RAM cell and drives a corresponding match line to a predetermined state when the comparand data and the stored data are matched. Examples of the binary CAM cells are disclosed in U.S. Pat. No. 4,646,271 entitled “CONTENT ADDRESSABLE MEMORY HAVING DUAL ACCESS MODE”, U.S. Pat. No. 4,780,845 entitled “HIGH DENSITY, DYNAMIC, CONTENT-ADDRESSABLE MEMORY CELL”, U.S. Pat. No. 5,490,102 entitled “LOW CAPACITANCE CONTENT-ADDRESSABLE MEMORY CELL”, and U.S. Pat. No. 5,495,382 entitled “CONTENTS ADDRESSABLE MEMORY”.
A TCAM cell can store one of three states of information, i.e., a logic “1” state, a logic “0” state, and a “don't care” state. The TCAM cell includes a main RAM cell to store one of two states of information, i.e., a logic “1” state or a logic “0” state, and a mask RAM cell to store local mask data. A comparison result of comparand data with data stored in the main RAM cell is masked with the mask data such that the comparison result does not affect a corresponding match line. Such a TCAM cell offers the user more flexibility to determine what data bits in a word will be masked during a compare operation. TCAM cells are further described, for example, in U.S. Pat. No. 6,044,055 entitled “CONTENT ADDRESSABLE MEMORY STORAGE DEVICE” and U.S. Pat. No. 6,514,384 entitled “TERNARY CONTENT ADDRESSABLE MEMORY CELL”.
FIG. 1
shows a conventional TCAM cell which includes a main memory cell having two NMOS transistors T
1
and T
2
and two inverters INV
1
and INV
2
, a compare circuit consisting of three NMOS transistors T
3
, T
4
, and T
5
, a mask circuit consisting of an NMOS transistor T
6
, and a mask memory cell consisting of two NMOS transistors T
7
and T
8
and two inverters INV
3
and INV
4
. The TCAM cell shown in
FIG. 1
is described in U.S. Pat. No. 6,154,384. Signal lines represented as “BL” and “BLB” are used for data transmission of a main memory cell. Signal lines represented as “CL” and “CLB” are used for comparand data transmission. Signal lines represented as “ML” and “MLB” are used for mask data transmission of a mask memory cell. A TCAM is made from TCAM cells arranged in a matrix of rows and columns. TCAM cells in a row constitute one word, which may be 32, 64, 128 bits, or higher. Transistors T
5
and T
6
of the respective TCAM cells in a row constitute a wired-OR logic for a match line MATCH.
Although TCAMS afford advantages such as speedy access for numerous applications, drawbacks do exist. For example, when comparand data of the TCAM cell of
FIG. 1
is not matched with data stored in a main memory cell, a discharge operation of a match line is carried out. Because the occurrence of unmatched words is usually greater than the occurrence of matched words, match lines (MATCH) corresponding to the unmatched words are frequently discharged, and more power is thereby consumed.
Another problem is shown in
FIG. 2A. A
logic high level at node DX of
FIG. 1
(VCL-Vtn4 or VCLB-Vtn3, wherein VCL represents a voltage of a CL line, VCLB represents a voltage of a CLB line, and the Vtn3 and Vtn4 represent threshold voltages of transistors T
3
and T
4
, respectively) approaches a voltage only slightly higher than the threshold voltage of transistor T
3
or T
4
. This high level voltage at DX is used to turn on transistor T
5
. To compensate for the lowered high voltage level, a big-sized transistor T
5
must be used. The need for a bigger size transistor in each cell lowers the overall density of the TCAM. Even more problematic, if an operation voltage is lowered, the TCAM cell may not operate properly as the high level voltage at DX fails to meet the threshold voltage of transistor T
5
. For illustration, assuming that an operation voltage is 1.2V and a threshold voltage of an NMOS transistor T
5
is 0.5V, a high level of the DX node thus becomes 0.7V, as shown in
FIGS. 2A and 2B
. Since this level is not high enough to turn on the NMOS transistor T
5
, the signal level on match line MATCH cannot be used to properly indicate a match or no-match.
Referring back to the TCAM cell of
FIG. 1
, if the compare result is not masked (by transistor T
6
), transistor T
5
is turned off when comparand data is matched to data stored in a main memory cell and is turned on when there is no match. That is, when there is a match, a match line MATCH is maintained at a precharge state. When there is no match, charges of the match line are discharged through transistors T
5
and T
6
. The discharge speed of the match line MATCH is a function of the number of unmatched bits in one word. For example, when only one bit of one word is unmatched, the charges of the match line MATCH are discharged through the transistors T
5
and T
6
of the unmatched TCAM cell. When n bits are unmatched among an m-bit word (n being a positive integer smaller than m), the charges of the match line MATCH are discharged through transistors nx (T
5
, T
6
) in n TCAM cells. The time needed to discharge the match line MATCH varies depending on the number of mismatched cells. To minimize the discharge speed variation, larger sized transistors T
5
and T
6
are needed. This, however, results in larger size TCAM cells. Therefore, a discharge speed difference also negatively affects the density of a TCAM.
In view of the foregoing, a need exists for a content addressable memory cell that is stably operable at low operation voltage, low power consumption, and facilitates manufacture of a high density CAM.
SUMMARY OF THE INVENTION
According to an aspect of the present invention, a ternary content addressable memory (TCAM) having an array of cells arranged in rows and columns is provided, each cell comprising: a main memory cell for storing a data bit and its complement and a pair of bit lines for carrying the data bit and its complement; a compare circuit having a pair of compare lines and an output node, the compare circuit coupled to the main memory cell for comparing the data bit and its complement with corresponding compare lines and outputting a compared signal at the output node; a match circuit coupled to the output node of the compare circuit and a match input line and a match output line, the match circuit for selectively connecting the match input line to the match output line based on the compared signal; a mask memory cell for storing and outputting mask data; and a mask circuit coupled to the match circuit and the match input line and the match output line for masking the compared signal or for selectively connecting the match input line to the match output line b

Affiliated with

Also associated with

Rating

Ternary content addressable memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Ternary content addressable memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ternary content addressable memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3364870