Process for fabricating a semiconductor device

Details Process for fabricating a semiconductor device Process for fabricating a semiconductor device

2002-11-01

2004-06-29

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

Reexamination Certificate

active

06756299

ABSTRACT:

CROSS REFERENCES TO RELATED APPLICATIONS
The present document is based on Japanese Priority Document JP 2001-343940, filed in the Japanese Patent Office on Nov. 9, 2001, the entire contents of which being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for fabricating a semiconductor device. More particularly, the present invention is concerned with a process for fabricating a semiconductor device having a multilayer wiring structure comprised of copper or the like as a material for wiring, which process enables reduction in both the number of steps and the wiring capacitance. In the present invention, the term “via hole” is a collective term for a contact hole, a via hole, and a through hole.
2. Description of Related Art
Recently, as a semiconductor device is scaled down and has an increased integration degree, the wiring in the semiconductor device is shrunk, causing reduction in the wiring pitch. Therefore, when a semiconductor device is produced by a process in which a wiring layer is formed on an insulating film and then patterned to form a wiring, the semiconductor device produced is likely to suffer wiring failure, such as burnout or short-circuiting.
For solving the problem, as a substitute for the process in which a wiring is formed on an insulating film, a so-called damascene process, in which a buried metal wiring is formed in an insulating film, has been practically used. Further, a dual damascene process comprising formation of an interconnection plug and formation of a wiring by a damascene process has also been practically used.
By the way, in accordance with further reduction in the wiring pitch, the wiring capacitance is increasing, and hence, it has been strongly desired to develop materials for wiring having a lowered electrical resistance and insulating films having a lowered dielectric constant. Therefore, it is attempted to use copper (Cu) as a substitute for aluminum (Al) which has been used as a material for wiring or to use insulating materials, such as organic materials including fluororesins, and xerogel, as a substitute for silicon oxide (SiO
2
) which has been used as an insulating film between wiring layers or between wirings. Organic materials including fluororesins, and xerogel are known as a low dielectric-constant insulating material having a dielectric constant as low as 3.0 or less.
An etching technique for copper has not yet been established, and therefore, the above-mentioned dual damascene process is inevitably used for utilizing copper as a material for wiring without any problem.
However, organic low dielectric-constant insulating materials have similar etching properties to those of a resist mask, especially they have almost the same etching rate as that of a resist mask, and hence, when copper is used as a material for wiring and a low dielectric-constant insulating material is used as an insulating film in the dual damascene process, it is difficult to use a resist as a mask for the low dielectric-constant insulating material. For this reason, when both copper and a low dielectric-constant insulating material are used in the dual damascene process, for obtaining a via hole and a wiring trench in communication with the via hole, a process is needed in which a wiring pattern is formed using a resist by a photolithography technique and the wiring pattern is transferred to an inorganic material film to form a so-called hard mask, and then a low dielectric-constant insulating material is etched using the hard mask.
Now, a process for forming a wiring for MOS transistor by a conventional dual damascene process is described below with reference to
FIGS. 3 and 4
.
FIGS. 3A
to
3
D and
FIGS. 4A
to E are diagrammatic cross-sectional views showing the successive steps in the formation of wiring by a conventional dual damascene process.
First, as shown in
FIG. 3A
, an interlayer dielectric
10
is formed from, for example, an organic insulating film on a substrate (not shown), and a wiring trench
12
is then formed in the interlayer dielectric
10
. Then, as a barrier metal, tantalum (Ta) is deposited on an inner wall of the wiring trench
12
so that the resultant thickness becomes 30 nm to form a refractory metal film
14
, and then a groove surrounded by the refractory metal film
14
is filled with a Cu wiring material
16
.
Subsequently, the Cu wiring material
16
is subjected to chemical mechanical polishing (hereinafter, frequently referred to simply as “CMP”) treatment to form a wiring layer (lower wiring)
16
, and then, on the interlayer dielectric
10
containing the wiring layer
16
, an insulating protecting film
18
, an interlayer dielectric
20
, and an interlayer dielectric
22
are formed in this order.
The protecting film
18
, the interlayer dielectric
20
, and the interlayer dielectric
22
can be formed, respectively, from SiN having a thickness of 50 nm, an organic low dielectric-constant insulating material having a thickness of 700 nm, and SiO
2
having a thickness of 200 nm.
Then, a photoresist
24
is applied onto the interlayer dielectric
22
, and then the photoresist
24
is exposed and developed to form a resist mask
24
having a wiring pattern for an upper wiring as shown in FIG.
3
B. Subsequently, the interlayer dielectric
22
is subjected to anisotropic etching using the resist mask
24
to transfer the wiring pattern for an upper wiring to the interlayer dielectric
22
as shown in FIG.
3
C.
Then, as shown in
FIG. 3D
, the resist mask
24
is removed to obtain an etching mask
22
A having the wiring pattern for an upper wiring. Then, as shown in
FIG. 4A
, a photoresist
26
is deposited onto the interlayer dielectric
20
having thereon the etching mask
22
A to form a resist mask
26
A having a via hole pattern
28
for the wiring layer
16
using a photolithography technique.
Next, as shown in
FIG. 4B
, part of the etching mask
22
A which protrudes in the via hole pattern
28
and the interlayer dielectric
20
are subjected to anisotropic etching using the resist mask
26
A. At a point in time when the thickness of the interlayer dielectric
20
on the protecting film
18
becomes, for example, 200 nm, the anisotropic etching is terminated to form part of a via hole
30
. Then, as shown in
FIG. 4C
, the resist mask
26
A is removed. Then, as shown in
FIG. 4D
, the interlayer dielectric
20
is subjected to anisotropic etching using the etching mask
22
A to form a wiring trench
32
in communication with the via hole
30
and the interlayer dielectric
20
is further etched through the via hole
30
so that the via hole
30
reaches the surface of the wiring layer
16
.
Then, as shown in
FIG. 4E
, Ta is deposited on the inner wall of each of the via hole
30
and the wiring trench
32
so that the resultant thickness becomes 30 nm to form a refractory metal film
34
, and then the groove surrounded by the refractory metal film
34
is filled with a Cu wiring material
36
. Then, the Cu wiring material
36
is subjected to CMP treatment to remove the excess Cu and excess refractory metal film
34
by polishing, thus forming a wiring layer
36
A and an interconnection plug
38
in the via hole
30
simultaneously. Subsequently, a sequence of the above-described dual damascene process is repeated in a desired frequency to obtain a MOS transistor having a dual damascene structure multilayer wiring.
For obtaining the etching mask
22
A by the above-described conventional dual damascene process, a plurality of steps, for example, (1) a step of forming the interlayer dielectric
22
, (2) a step of depositing the photoresist
24
, (3) a step of forming the resist mask
24
, (4) a step of transferring a wiring pattern to the interlayer dielectric
22
, and (5) a step of removing the resist mask
24
are required.
Therefore, the fabrication process needs a large number of steps, so that the process becomes complicated, leading to problems in that the cost for producing LSI having a MOS transistor is increased, and

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