Method for forming silicide at source and drain

Details Method for forming silicide at source and drain Method for forming silicide at source and drain

2003-03-26

2004-06-01

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S649000, C438S682000

Reexamination Certificate

active

06743717

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming silicide, and in particular to a method that forms silicide at source and drain using the barrier layer to conceal areas where silicide is not required.
2. Description of the Related Art
FIG. 1
illustrates a current process for fabricating integrated circuits. Firstly, a plurality of gates
12
C and
12
S are formed respectively on the cell region and peripheral region of a semiconductor substrate
10
. Then, spacers
14
of dielectric material are formed on two sides of the gates
12
C and
12
S. Next, ion implantation is carried out to form source S and drain D on two sides of the gate
12
C at the cell region (C) and on two sides of the gate
12
S in the peripheral region (S). A barrier layer
16
, usually SiN, is then formed conformally to cover the gates
12
C and
12
S, followed by formation of an interlayer dielectric (ILD) layer
18
.
Due to the ongoing reduction of the sizes of integrated circuits (ICs), the contact resistance and sheet resistance at the source/drain and gates have brought more and more apparent adverse effects to the performance of semiconductor elements. In order to effectively reduce contact resistance and sheet resistance to avoid reduction of saturate current caused by excess contact resistance and sheet resistance, there has been a method proposed to form silicide only in areas that require them so that sheet resistance is reduced. This method starts with the formation of an oxide layer to cover gates. A mask layer is then formed to cover the region not requiring silicide, followed by etching to expose the area that does. This method is advantageous in reducing sheet resistance.
However, the above method requires the formation of another oxide layer, and the deposition of the oxide easily causes problems in filling the cell region. As a result, there is a need for a method able to reduce both sheet resistance and contact resistance without the conventional shortcomings.
SUMMARY OF THE INVENTION
Accordingly, an object of the invention is to provide a method for forming silicide at source and drain using the current barrier layer with the addition of a mask layer, followed by photolithography and etching to protect the area not requiring silicide, thus forming silicide at source and drain. Both sheet resistance and contact resistance are thereby reduced.
The method to form silicide at source and drain provided in the present invention comprises providing a semiconductor substrate having an active region and peripheral region, wherein gates with source and drain on the sides are formed in the peripheral region, conformally forming a barrier layer to cover the active region and the peripheral region, forming a mask layer to cover the barrier layer at the active region, removing the barrier layer covering the peripheral region; removing the mask layer; forming a metal layer to cover the peripheral region, and subjecting the metal layer to thermal process so that silicon reacts with the metal to form silicide at the source and the drain.
A detailed description is given in the following embodiments with reference to the accompanying drawings.


REFERENCES:
patent: 6025267 (2000-02-01), Pey et al.

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