Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-03-12
2004-06-15
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257SE27104
Reexamination Certificate
active
06750493
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-067496, filed Mar. 12, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor storage device, and in particular, to a nonvolatile ferroelectric memory.
2. Description of the Related Art
Today, semiconductor memories are utilized in various applications, including main memories of large-scale computers as well as personal computers, electric appliances, and cellular phones. Semiconductor memories on the market include volatile DRAMs (Dynamic Random Access Memories), SRAMs (Static Random Access Memories), nonvolatile MROMs (Mask Read Only Memories), and Flash EEPROM (Flash Electrically Erasable and Programmable Read Only Memories).
In particular, the DRAM is a volatile memory but is excellent in cost (its cell area is a quarter of that of an SRAM) and speed (it operates faster than a Flash EEPROM). Thus, DRAMs now occupy the largest market share.
Further, a rewritable nonvolatile Flash EEPROM is nonvolatile and thus its power supply can be turned off. However, the number of times this Flash EEPROM can be rewritten (the number of W/Es) is only about 10
6
. It takes microseconds to write data in the Flash EEPROM. Furthermore, a high voltage (12V to 22V) must be applied to achieve writes. The Flash EEPROM has such advantages, so that the percentage of the market taken up by the Flash EEPROM is now smaller than that taken up by the DRAM.
In contrast, since a nonvolatile ferroelectric memory employing a ferroelectric capacitor was proposed in 1980, many manufacturers have been making efforts to develop this memory. This is because it is nonvolatile, the number of times it can be rewritten is 10
12
, and it can operate at 3V to 5V, etc.
FIG. 1A
shows a memory cell in a conventional ferroelectric memory which is composed of one transistor and one capacitor, and a cell array configuration in this memory.
In the memory cell configuration of the conventional ferroelectric memory, a transistor CT and a capacitor FC are connected together in series. The following components are arranged in the cell array: bit lines BL and/BL through which data is read, word lines WL
0
and WL
1
through which the memory cell transistor CT is selected, and plate lines PL
0
and PL
1
that drive one end of the ferroelectric capacitor FC. Furthermore, plate line driving circuits PLD
0
and PLD
1
are connected to the plate lines PL
0
and PL
1
, respectively.
However, this conventional ferroelectric memory has a folded bit line configuration in which one memory cell is arranged per two intersections of the word lines and bit lines, as shown in FIG.
1
B. When both interconnect width and interconnect space are defined as F, the minimum cell size is limited to 2F×4F=8F
2
. Thus, disadvantageously, the cell size of the conventional ferroelectric memory is limited to 8F
2
.
Further, in the conventional ferroelectric memory, to prevent destruction of polarization information in the ferroelectric capacitors of non-selected memory cells, the plate lines must be separated from one another so as to correspond to the respective word lines, and must be individually driven. Furthermore, a plurality of ferroelectric capacitors are connected to each plate line in the direction of the word lines. Consequently, the plate line has a large load capacity. Moreover, the pitch with which the plate line driving circuits are arranged must be similar to that with which the word lines are arranged. It is thus impossible to increase the size of each plate line driving circuit. Accordingly, it takes much time to increase or reduce the potential across the plate line. Therefore, the ferroelectric memory operates at low speed.
To solve this problem, the inventor has proposed in Jpn. Pat. Appln. KOKAI Application No. 10-255483,Jpn. Pat. Appln. KOKAI Application No. 11-177036, and Jpn. Pat. Appln. KOKAI Application No. 2000-22010, all of which have been previously filed, a new nonvolatile ferroelectric memory featuring three points that are compatible with one another: (1) small memory cells of size 4F
2
, (2) planar transistors that can be easily manufactured, and a (3) general-purpose fast random access function.
FIG. 1C
shows a configuration of the ferroelectric memory according to the previous applications.
As shown in
FIG. 1C
, in this ferroelectric memory, one memory cell is composed of the cell transistor CT and ferroelectric capacitor FC connected together in parallel. One memory cell block MCB is composed of a plurality of parallel-connected memory cells connected together in series. One end of the memory cell block MCB is connected to the bit line BL via a block selection transistor BST. The other end is connected to the plate line PL. Furthermore, the plate line driving circuit PLD is connected to the plate line PL. With this configuration, planar transistors can be used to realize a memory cell
101
with the minimum size of 4F
2
as shown in FIG.
1
D.
The ferroelectric memory shown in
FIG. 1C
operates as described below. A memory cell transistor and ferroelectric capacitor in a memory cell from which data is to be read are defined as CT
1
and C
1
, respectively. Memory cell transistors and ferroelectric capacitors in other memory cells are defined as CT and FC, respectively. As shown in
FIG. 2A
, during standby, all word lines WL
0
to WL
3
are set at a “high” potential, and the memory cell transistors CT and CT
1
are turned on. Furthermore, a signal interconnect BS
0
of a block selection transistor BT
0
is set at a “low” potential, with the block selection transistor BT
0
turned off. Then, the opposite ends of each of the ferroelectric capacitors FC and C
1
are electrically shorted by a corresponding one of turned-on cell transistors CT and CT
1
. Thus, no difference in potential occurs across each of the ferroelectric capacitors FC and C
1
. Storage polarization is therefore stably retained.
FIG. 2B
shows a hysteresis curve for the polarization capacity of the ferroelectric capacitor during standby.
Further, in operation, only the memory cell transistor connected together in parallel to a ferroelectric capacitor from which data is to be read is turned off. The other memory cell transistors are turned on. Furthermore, the block selection transistor is turned on.
For example, as shown in
FIG. 2C
, if the ferroelectric capacitor C
1
is to be selected which belongs to the ferroelectric memory cell composed of the memory cell transistor CT
1
and this ferroelectric capacitor C
1
, then the word line W
2
is set to the “low” potential. Subsequently, the plate line PL is set to the “high” potential. The signal interconnect BS
0
of the block selection transistor BT
0
is set to the “high” potential. Then, the difference in potential between the plate line PL and the bit line BL is applied only to the opposite ends of the ferroelectric capacitor C
1
, connected together in parallel to the memory cell transistor CT
1
, which has been turned off. Polarization information on the ferroelectric capacitor C
1
is read out to the bit line BL.
FIG. 2D
shows a hysteresis curve of polarization capacity of the ferroelectric capacitor during operation.
Thus, even if the memory cells are connected together in series, selecting an arbitrary word line enables cell information to be read from an arbitrary ferroelectric capacitor. This serves to accomplish perfect random accesses. Further, the plate line can be shared by a plurality of memory cells. The area of the plate line driving circuit can thus be increased, while reducing chip size. Therefore, high-speed operations can be realized.
However, the ferroelectric memory shown in
FIG. 1C
also has problems described below. As disclosed in Jpn. Pat. Appln. KOKAI Publication No. 11-177036, a ferroelectric memory of a folded bit line configuration can be actualized by providing two types of si
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