Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-08-22
2004-11-09
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S330000
Reexamination Certificate
active
06815758
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to a structure and method of fabricating a semiconductor device. More particularly, the present invention relates to a structure and method of fabricating a flash memory cell.
2. Description of Related Art
A typical flash memory cell includes a stacked structure of a control gate and a floating gate, and a source/drain region on two sides of the structure, where the control gate and the floating gate are generally constructed of polysilicon. In a conventional method of process of a flash memory cell, a positive high voltage is applied, in a programming mode, to a control gate to cause electrons injecting to a floating gate so that the channel under the floating gate is turned off in a reading operation; while a negative high voltage is applied, in an erasing mode, to the control gate to cause electrons ejecting from the floating gate so that the channel under the floating gate is turned on in a reading operation. Data in the memory cell are judged by whether the channel is turned on.
However, over-erase often occurs in a process to erase a flash memory cell. In other words, too much electrons eject from the floating gate to cause the floating gate carrying positive charges, and thus the channel under the floating gate will have electron leakage; when the over-erase becomes more significant, the channel may even stay in an on-state to seriously interfere reading operation of other memory cells. To solve such problems, prior art provides a split-gate design, i.e., by constructing a select gate beside the floating gate and separating the select gate from a substrate with a gate oxidation layer, under which another channel for the memory cell is formed. Thus, when the channel under the floating gate continues to be turned on due to over-erase, the select gate beside the floating gate will have a function to turn on or off the channel of the memory cell. The select gate is mostly constructed of polysilicon and is patterned simultaneously with the control gate.
Even though the split-gate design in prior art may effectively avoid problems caused by over-erase, the split gate fabricating process requires two deposition steps to deposit polysilicon and thus is time consuming since the select gate is formed after the formation of the floating gate.
SUMMARY OF INVENTION
The present invention is to provide a structure of a flash memory cell with a split-gate design to avoid various problems caused by over-erase of the floating gate, and formation of the structure requires only a single step of polysilicon deposition.
The present invention is also to provide a fabricating method which requires only a single step of polysilicon deposition in the process to form the split gate for saving time and costs.
The flash memory cell of the present invention includes a substrate, a select gate, a floating gate, a gate dielectric layer, a high-voltage doped region and a source region. There is a first opening in the substrate and further, there is a second opening on the bottom of the first opening in the substrate. The second opening is narrower than the first opening, while the second opening is deeper, as measured from the surface of the substrate, than the first opening. The select gate is on the sidewall of the first opening, and the floating gate is on the sidewall of the second opening. The gate dielectric layer is between the select/floating gates and the substrate. The high-voltage doped region is under the bottom of the second opening in the substrate, and the source region is formed besides the first opening in the substrate. The high-voltage region is simultaneously used as control gate and drain region.
The above flash memory cell of the present invention can further include an insulating layer and a contact plug, where the insulating layer is on the top of the substrate and covers the select gate and the floating gate. The contact plug penetrates through the insulating layer and is electronically connected to the high-voltage doped region to supply high voltage to the high-voltage doped region.
The method of fabricating the flash memory cell of the present invention includes the following steps. First, a substrate is provided and a first opening and a second opening are formed in the substrate, where the second opening is formed on the bottom of the first opening in the substrate. The second opening is narrower than the first opening, while the second opening is deeper, as measured from the surface of the substrate, than the first opening. A high-voltage doped region is formed under the bottom of the second opening in the substrate, and a gate dielectric layer is formed on the substrate in the first and the second openings. A first conductive spacer is formed as a select gate on the sidewall of the first opening, and a second conductive spacer is formed as a floating gate on the sedewall of the second opening. Additionally, a source region is formed in the substrate beside the first opening.
Furthermore, in the above fabricating process of the flash memory cell of the present invention, after the formation of the source region, an insulating layer is formed on the substrate to cover the select gate and the floating gate. A contact plug, which penetrates through the insulating layer and is electronically connected to the high-voltage doped region, can also be formed to supply high voltage in the high-voltage doped region.
As mentioned above, in the fabricating process of the flash memory cell of the present invention, the select gate and the floating gate are simultaneously formed on the sidewalls of the first and the second openings, respectively. Consequently, the fabricating process requires only a single deposition step to form the select gate and the floating gate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6137132 (2000-10-01), Wu
Chang Ko-Hsing
Hsu Hann-Jye
Jiang Chyun IP Office
Nelms David
Nguyen Thinh T
Powerchip Semiconductor Corp.
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