Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2001-06-12
2004-11-30
Baderman, Scott (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S725000
Reexamination Certificate
active
06826717
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to analysis and debugging of integrated circuit devices. More specifically, the present invention relates to synchronizing the debugging of a processor and a PLD embedded on a common chip.
BACKGROUND OF THE INVENTION
Since their inception, digital systems have progressed towards higher levels of integration. Higher integration produces several benefits including increased performance and lower development costs. At the device level integration has been achieved by combining functions once performed by multiple individual devices into higher density devices with greater capabilities.
Architectural and process enhancements as well as incorporation of memory onboard the microprocessor chip have permitted microprocessors to operate at higher speeds and with greater capabilities. Likewise, programmable logic devices have matured to meet customer's expectations of greater capacity and performance through increases in size and density and by changes in architecture. Programmable logic devices refer to any integrated circuit that may be programmed to perform a desired function and include programmable logic arrays (PLAs), programmable array logic (PAL), field programmable gate arrays (FPGA), complex programmable logic devices (CPLDs), and a wide variety of other logic and memory devices that may be programmed. The increased size and capabilities of the devices, with their corresponding complexities, has resulted in movement towards higher levels of abstraction in the design development of microprocessors and programmable logic devices. Programming languages used in conjunction with the design development of microprocessor circuits have evolved towards languages using higher levels of abstraction, such as C, C++, and JAVA. High level hardware description languages, including Verilog and VHDL, are typically employed to develop designs in programmable logic devices. The increased complexity of these devices has also resulted in increased reliance on design verification through on-chip debugging tools. Such tools as Background Debug Mode, Enhanced JTAG, and N-Wire are used in debugging microprocessors.
Traditional design approaches include combining a microprocessor with off-the-shelf devices on a system board. This approach presents problems such as increased delay from signals travelling off chip to other devices and increased power consumption. On the other hand, integrating an embedded processor with programmable logic within a PLD provides several advantages in addition to increased performance. Flexibility is given to the designer to determine which functions should be executed in software (by the processor) and which would benefit form hardware implementation in the PLD. Debugging such a system on a programmable chip (“SOPC”) presents unique problems best described after a more detailed description of conventional debugging approaches for PLD's and microprocessors (software debugging).
In the field of electronics, various electronic design automation (EDA) tools are useful for automating the process by which integrated circuits, multi-chip modules, boards, etc., are designed and manufactured. In particular, electronic design automation tools are useful in the design of standard integrated circuits, custom integrated circuits (e.g., ASICs), and in the design of custom configurations for programmable integrated circuits. Integrated circuits that may be programmable by a customer to produce a custom design for that customer include programmable logic devices (PLDs). Often, such PLDs are designed and programmed by a design engineer using an electronic design automation tool that takes the form of a software package. These tools commonly offer the designer the option of inputting the design in at least one high level hardware description language.
In the course of generating a design for a PLD, programming the PLD and checking its functionality on the circuit board or in the system for which it is intended, it is important to be able to debug the PLD because a design is not always perfect the first time. Before a PLD is actually programmed with an electronic design, a simulation and/or timing analysis may be used to debug the electronic design. However, once the PLD has been programmed and is operating within a working system, it is also important to be able to debug the PLD in this real-world environment.
And although a simulation may be used to debug many aspects of a PLD, it is nearly impossible to generate a simulation that will accurately exercise all of the features of the PLD on an actual circuit board operating in a complex system. For example, a simulation may not be able to provide timing characteristics that are similar to those that will actually be experienced by the PLD in a running system; e.g., simulation timing signals may be closer or farther apart than what a PLD will actually experience in a real system.
In addition to the difficulties in generating a comprehensive simulation, other circuit board variables such as temperature changes, capacitance, noise, and other factors may cause intermittent failures in a PLD that are only evident when the PLD is operating within a working system. Still further, it can be difficult to generate sufficiently varied test vectors to stress the PLD design to the point where most bugs are likely to be observed. For example, a PLD malfunction can result when the PLD is presented with stimuli that the designer did not expect, and therefore did not take into account during the design and simulation of the PLD. Such malfunctions are difficult to anticipate and must be debugged in the context of the complete system. Thus, simulation of an electronic design is useful, but usually cannot debug a PLD completely.
One approach to debugging a hardware device within a working system is to use a separate piece of hardware equipment called a logic analyzer to analyze signals present on the pins of a hardware device. (For example, the HP1670A Series Logic Analyzer from Hewlett-Packard Company.) Typically, a number of probe wires are connected manually from the logic analyzer to pins of interest on the hardware device in order to monitor signals on those pins. The logic analyzer captures and stores these signals. However, the use of an external logic analyzer to monitor pins of a hardware device has certain limitations when it comes to debugging such a device. For example, such an external logic analyzer can only connect to and monitor the external pins of the hardware device. Thus, there is no way to connect to and monitor signals that are internal to the hardware device. Unfortunately, when programming a hardware device such as a PLD, it would be useful to be able to monitor some of these internal signals in order to debug the PLD.
Although some custom hardware devices may come ready made with some internal debugging hardware, this debugging hardware is typically hardwired to route specific internal signals and cannot be readily changed by an engineer who wishes to look at other signals. Also, with such built-in debugging it is not possible to choose any signal to monitor that the engineer desires, nor can triggering signals and triggering conditions be changed by the engineer. Because a PLD by its very nature is a programmable device that an engineer is attempting to program to perform a particular function, it is important to the engineer to be able to customize monitored signals, trigger signals, and trigger conditions in order to efficiently debug any particular device. Further, creating an electronic design for a PLD is an iterative process that requires creative debugging by an engineer who may wish to view almost any internal signal, and who may change his mind fairly frequently in the course of debugging a PLD within a system. Known external and internal logic analyzers do not provide this flexibility.
A further drawback to using an external logic analyzer or hardwired predetermined debugging hardware inside of a custom chip is that often the number of interna
Draper Andrew
Flaherty Edward
Altera Corporation
Baderman Scott
Beyer Weaver & Thomas LLP.
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