Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-06-10
2004-08-10
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06775806
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to integrated circuit development, and more specifically to a design environment for computer-aided integrated circuit development.
A typical development process for integrated circuits can be generally divided into a front-end design phase and a back-end development phase. During the front-end phase, the engineer user designs and develops, from a set of specifications, a logical representation of the integrated circuit of interest in the form of a schematic. With the aid of integrated circuit test tools available, an engineer may test the design of the integrated circuit. For example, the operation of the integrated circuit design may be emulated.
The back-end development involves several steps during which a final circuit layout (physical description) is developed based on the schematic. During the back-end development various building blocks (or cells) as defined by the finalized integrated circuit schematic are placed within a predefined floor plan. For integrated circuit designs based on array or standard cell technology, the various circuit building blocks are typically predefined and made available to a computer from a cell library stored remotely with respect thereto e.g., on a server. As a result, each cell may correspond to one or more electrical functions, e.g., resistor, capacitor, differential operational amplifier, J-K flip-flop and the like. Placement is followed by a routing, during which interconnects between cells are routed throughout the layout. Finally, the accuracy of the layout versus the schematic is verified, with the aid of integrated circuit test tools available to the client terminal from the server.
A well known suite of integrated circuit design and test tools is DESIGN FRAMEWORK II® (DFII) available from CADENCE®. DFII provides a common user interface and a common database for the design tools included in the suite. This avoids having to translate the database files when working with the differing tools in the suite. To that end, the data associated with a particular integrated circuit design are organized in libraries. The libraries consist of cells that are a database object that contains information concerning the basic building blocks of an integrated circuit, e.g., metal, inverter, resistor, via, etc. The libraries are associated with a Technology File that includes information concerning the design rules and electrical functions that an integrated circuit must satisfy.
Referring to
FIG. 1
, a typical design flow employed using DFII includes creating a schematic of the cells associated with an integrated circuit design at step
10
. This may be performed employing the VIRTUOSO SCHEMATIC COMPOSER® tool included with DFII. At step
12
, schematic is analyzed by a different tool associated with DFII, such as AFFIRMA SPECTRE CIRCUIT SIMULATOR®. This tool simulates the operation of the circuit and determines operational characteristics of the same. After determining that the schematic operated in accordance with the associated technology file, at step
14
, the layout of the integrated circuit is performed. The integrated circuit may be laid-out using another tool associated with DFII, such as VIRTUOSO LAYOUT EDITOR®. At step
16
, verification of the layout is achieved using another tool to identify violations of geometric or electrical rules, as well as to verify the function of the physical implementation.
The DIVA® verification tool provides numerous commands and modifiers to develop Design Rule Checks (DRC) that verify adherence to fabrication design rules associated with Technology Files. The DIVA® verification tool also allows recognition and extraction of device parameters from all integrated circuit technologies. To that end, predefined device descriptions are included that greatly reduce the time for extraction of the device parameters. Also, electrical-connectivity check on both logical and physical network representations may be performed using the DIVA® verification tool. Complete control over the parameters being checked is afforded, e.g., whether parameters must be matched exactly or be within a certain range.
Operation of DFII is regulated by control software, such as the SKILL® programming language. Specifically, commands and internal communication with and between the tools associated with DFII occurs through the use of SKILL®. SKILL® is available to the Engineers using DFII to create scripts for performing various tasks with the DFII. Difficulty arises, however, in fully integrating SKILL® programming language with the various tools associated with DFII so that the full power of the DFII can be realized to reduce the time required to design an integrated circuit. Specifically, to perform the verification of an integrated circuit design, SKILL® is employed to create a plurality of rules files. Each rules file includes a sequence of commands required for DIVA® to determine whether an integrated circuit design satisfies design rules. To that end, for each feature verified, every rules file must be called by DIVA® to ensure that the pertinent design rules are analyzed for the feature being verified. Alternatively, the appropriate rules files contained in a database of rules files are identified and invoked by DIVA®, manually by a design engineer. Both of these methods of verification are time-consuming and tedious.
A need exist, therefore, to provide an improved method, a system and a computer product, to generate and verify integrated circuit designs on computers while by fully integrating design tools associated with the tool suite.
SUMMARY OF THE INVENTION
The present invention provides a method, a system and a computer product for designing an integrated circuit using a computer having a memory that features dynamically generating rules files to verify adherence of an integrated circuit design with design rules. To that end, a method in accordance with one embodiment of the present invention includes mapping the integrated circuit into various addresses of the memory as multiple production layers. The multiple production layers include a plurality of data objects. The addresses in memory corresponding to the locations in one of the multiple production layers are identified where data object characteristics are to be varied. These addresses are referred to as varied object addresses. The data object characteristics stored at the varied object addresses are varied, defining varied data objects. Information concerning the varied data objects is stored in the memory addresses associated with a construction layer. This information includes the varied object addresses. A rules file is generated and loaded into the memory, at addresses different from the varied object addresses. The rules file includes a sequence of commands to analyze the data object characteristics stored at the varied object addresses to determine whether characteristics of the varied data objects satisfy design rules. The commands associated with the sequence are dependent upon the production layer with which the varied objects are associated, as well as the objects being varied. Then, varied data objects having characteristics that violate the design rules are distinguished from data objects having characteristics that satisfy the design rules. Also included are a system and a computer product that functions in accordance with the method.
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Jagasiv
Siek Vuthe
Sun Microsystems Inc.
Zagorin O'Brien & Graham LLP
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