Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2002-01-02
2004-08-10
McLean-Mayo, Kimberly (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S105000, C713S400000, C713S401000, C713S500000, C713S501000, C713S503000, C713S601000
Reexamination Certificate
active
06775755
ABSTRACT:
TECHNICAL FIELD
This invention relates to coupling signals from one electronic device or circuit to another, and more particularly to coupling signals between electronic devices or circuits having different clock domains defined by respective clocks that may differ in phase from each other.
BACKGROUND OF THE INVENTION
Many electronic devices operate in a synchronous manner in which the timing of signals in the device are controlled by a clock signal. The transitions of the clock signal occur at substantially the same time throughout the circuit, thereby ensuring that signals coupled or created responsive to the transitions of the clock signal are properly synchronized to each other.
Although synchronism between signals can be maintained when the same clock signal, or clock signals derived from the same clock signal, are used throughout a circuit. It is substantially more difficult to properly synchronize signals coupled from one electronic device to another when the electronic devices operate in different clock domains defined by respective clock signals having phases that may differ from each other in some unpredictable or uncontrolled manner.
One example of an electronic device in which signals must be coupled between circuits operating in different clock domains is a packetized dynamic random access memory (“DRAM”), using Synchronous Link DRAM (“SLDRAM”) architecture. An example of a SLDRAM is shown in FIG.
1
. With reference to
FIG. 1
, the SLDRAM
16
includes a clock generator circuit
40
that receives a command clock signal CMDCLK and generates an internal clock signal ICLK, a data clock signal DCLK, a write clock signal WCLK, and a large number of other clock and timing signals to control the timing of various operations in the SLDRAM
16
. The SLDRAM
16
also includes a command buffer
46
and an address capture circuit
48
, which receive the internal clock signal ICLK, a command packet CA
0
-CA
9
on a 10-bit command bus
50
, and a FLAG signal on line
52
. A memory controller (not shown) or other device normally transmits the command packet CA
0
-CA
9
to the SLDRAM
16
in synchronism with the command clock signal CMDCLK. The command packet, which generally includes four 10-bit packet words, contains control and address information for each memory transfer. The FLAG signal identifies the start of a command packet, and it also signals the start of an initialization sequence. The command buffer
46
receives the command packet from the bus
50
, and compares at least a portion of the command packet to identifying data from an ID register
56
to determine if the command packet is directed to the SLDRAM
16
or another SLDRAM
16
. If the command buffer
46
determines that the command packet is directed to the SLDRAM
16
, it then provides the command words to a command decoder and sequencer
60
. The command decoder and sequencer
60
generates a large number of internal control signals to control the operation of the SLDRAM
16
during a memory transfer.
The phase of the ICLK signal relative to the CMDCLK signal is determined during an initialization procedure. As described more fully in U.S. patent application Ser. No. 08/890,055 to Baker et al, which is incorporated herein by reference, a memory controller (not shown) repeatedly applies packet words to the SLDRAM
16
. The memory device attempts to capture these packet words in the command buffer
46
using a variety of different phases of the ICLK signal relative to the phase of the CMDCLK signal received from the memory controller. The memory device then determines which phase of the ICLK signal was best able to capture the packet words, and uses this phase during normal operation of the SLDRAM
16
.
The address capture circuit
48
also receives the command words from the command bus
50
and outputs a 20-bit address corresponding to the address information in the command packet. The address is provided to an address sequencer
64
, which generates a corresponding 3-bit bank address on bus
66
, a 10-bit row address on bus
68
, and a 7-bit column address on bus
70
. The column address and row address are processed by column and row address paths
73
,
75
as will be described below.
One of the problems of conventional DRAMs is their relatively low speed resulting from the time required to precharge and equilibrate circuitry in the DRAM array. The SLDRAM
16
shown in
FIG. 1
largely avoids this problem by using a plurality of memory banks
80
, in this case eight memory banks
80
a-h
. After a read from one bank
80
a
, the bank
80
a
can be precharged while the remaining banks
80
b-h
are being accessed. Each of the memory banks
80
a-h
receives a row address from a respective row latch/decoder/driver
82
a-h
. All of the row latch/decoder/drivers
82
a-h
receive the same row address from a predecoder
84
which, in turn, receives a row address from either a row address register
86
, redundant row circuit
87
, or a refresh counter
88
as determined by a multiplexer
90
. However, only one of the row latch/decoder/drivers
82
a-h
is active at any one time as determined by bank control logic
94
as a function of a bank address from a bank address register
96
.
The column address on bus
70
is applied to a column latch/decoder
100
, which supplies I/O gating signals to an I/O gating circuit
102
. The I/O gating circuit
102
interfaces with columns of the memory banks
80
a-h
through sense amplifiers
104
. Data is coupled to or from the memory banks
80
a-h
through the sense amplifiers
104
and I/O gating circuit
102
and a data path subsystem
108
, which includes a read data path
110
and a write data path
112
. The read data path
110
includes a read latch
120
that stores data from the I/O gating circuit
102
. In the SLDRAM
16
shown in
FIG. 1
, 64 bits of data are stored in the read latch
120
. The read latch then provides four 16-bit data words to an output multiplexer
122
that sequentially supplies each of the 16-bit data words to a read FIFO buffer
124
. Successive 16-bit data words are clocked into the read FIFO buffer
124
by the data clock signal DCLK generated by the clock generator circuit
40
. As explained below, the DCLK signal is also coupled to the memory controller or other device that receives the data read from the SLDRAM
16
.
The phase of the DCLK signal relative to the CMDCLK signal, like the phase of the ICLK signal, is determined during the initialization procedure. The memory controller (not shown) determines which phase of the DCLK signal will cause the DCLK signal as received by the memory controller to be in phase with the CMDCLK signal that the memory controller applies to the SLDRAM
16
. The memory controller then applies a packet to the SLDRAM
16
that causes the clock generator
40
to use the selected phase of the DCLK signal during normal operation of the memory device. As a result, the memory controller can operate in a single clock domain regardless of which of several memory devices it is accessing.
The read FIFO buffer
124
operates in a clock domain corresponding to the DCLK signal. On the other hand, the command buffer
46
, the command decoder and sequencer
60
, and the memory arrays
80
a-h
operate in a clock domain corresponding to the ICLK signal. The phase of the DCLK signal relative to the phase of the ICLK signal selected during the initialization procedure will vary in an unpredictable and uncontrollable manner since they will depend upon such factors as signal path lengths and the operating speed of various circuits in the SLDRAM
16
and the memory controller. As a result, the read FIFO buffer
124
operates in a clock domain that is different from the clock domain in which the command buffer
46
, the command decoder and sequencer
60
, and the memory arrays
80
a-h
operate.
After each 16-bit word is clock into the read FIFO buffer
124
, it is clocked out of the read FIFO buffer
124
by a RCLK clock signal obtained by coupling the DCLK signal through a programmable delay circuit
126
. The programmable delay cir
Dorsey & Whitney LLP
McLean-Mayo Kimberly
Micro)n Technology, Inc.
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