Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-16
2004-06-01
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S377000, C257S412000, C257S510000, C438S172000, C438S178000
Reexamination Certificate
active
06744104
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor integrated circuit including an insulated gate field effect transistor (hereinafter called “IGFET”), and a method of manufacturing the same, and more particularly to a semiconductor integrated circuit including an IGFET which is constituted by a gate electrode having regions composed of two or more IV group elements which are different from each other, and a method of manufacturing the same. More specifically, the invention relates to a semiconductor integrated circuit including an elevated or raised source drain electrode in a main electrode which is used as a source or drain electrode of an IGFET, and a method of manufacturing the same.
2. Description of the Related Art
As a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) for constituting a semiconductor integrated circuit is being minimized, a gate insulated film of the MOFET tends to be made much thinner. Further, in order to suppress short channel effect due to minimization, a complementary MOSFET tends to adopt a dual gate structure for an electrode. In the dual gate electrode structure, a gate electrode of an n-channel MOSFET is set to an n-type while a gate electrode of a p-channel MOSFET is set to a p-type.
The electrode having the dual gate structure is generally manufactured by a process for manufacturing ordinary complementary MOSFET (CMOS) without an increase in the number of manufacturing processes. Specifically, in an n-channel MOSFET, an n-type impurity is doped in order to make source and drain electrodes for an n-type semiconductor region. Simultaneously, the n-type impurity is doped into a gate electrode. With a p-channel MOSFET, a p-type impurity is doped so as to make source and drain electrodes for a p-type semiconductor region. Concurrent with this, the same p-type impurity is doped into a gate electrode. Ion implantation is performed for the doping process. The doped gate electrode is annealed in order that the doped impurity is diffused and activated. The gate electrode doped by the n-type impurity is set to the n-type while the gate electrode doped by the p-type impurity is set to the p-type.
As the MOSFET is being minimized, the source and drain electrodes thereof are required to be made shallow and to have low resistivity. An elevated electrode structure is most preferable in order to meet the foregoing requirements. In the elevated electrode structure, elevated electrodes are laid over a source electrode (a semiconductor region) and a drain electrode (a semiconductor region) on a surface of a substrate made of single crystal Si (silicon). Each elevated electrode is formed by an epitaxial growth layer grown on the single crystal Si substrate. The source and drain electrodes are formed by diffusing an impurity over the single crystal Si substrate using the elevated electrodes as solid diffusion sources.
In the foregoing structure, the source and drain electrodes are formed through diffusion from the surface of the single crystal Si substrate, so that a shallow junction can be obtained. Further, one elevated electrode is laid over the source electrode, and the other elevated electrode is laid over the drain electrode. Therefore, it is possible to reduce resistivity of the electrodes.
However, the following considerations have not been taken in the semiconductor integrated circuit including the foregoing MOSFET.
(1) Use of the dual gate electrode structure causes different problems in the n-channel MOSFET and p-channel MOSFET, respectively. In the p-channel MOSFET, when forming source electrode and drain electrode having shallow junctions, ion implantation is executed using BF
2
(boron fluoride) ions which can accomplish shallow ion implantation distribution (profile) In such a case, F (fluoride) which is ion-implanted simultaneously with B (boron) infiltrates into a gate insulated film (gate oxide film), and promotes diffusion of B in the gate insulated film, so that B leaks through the substrate (channel forming region) from the gate electrode. Thinning of the gate insulated film due to the minimization enhances leakage of B. Even if there is no F, leakage of B occurs because of the thin insulated gate film. As a result, a threshold voltage of the p-channel MOSFET becomes variable, which unfortunately reduces electrical reliability of a semiconductor circuit.
Conversely, in the n-channel MOSFET, when forming source and drain electrodes having shallow junctions, As (arsenic) ions which diffuse slowly are used. In order to prevent an increase in the number of manufacturing processes, the source and drain electrodes are doped by As ions as an n-type impurity, similarly to the gate electrode. The As ions are suitable to form source and drain electrodes having shallow junctions (i.e. in order to make the source and drain electrodes shallow). However, a low diffusion speed of As makes it difficult for As to diffuse all over the gate electrode with a high concentration, which means that the gate insulated film of the gate electrode suffers from an insufficient As concentration. Especially, shallow source and drain electrodes tend to be annealed at a low temperature, which further promotes the insufficient As concentration on the gate insulated film of the gate electrode. Therefore, when gate bias is applied to the gate electrode during actual operation, a depletion layer is produced in the gate electrode, and a threshold voltage of the n-channel MOSFET is made variable. This inevitably lowers electrical reliability of the semiconductor integrated circuit.
(2) The lowered electrical reliability of the semiconductor integrated circuit is an obstacle for minimization of the MOSFET, and prevents further integration of the semiconductor integrated circuit.
(3) Japanese Patent Laid-Open Publication No. Hei 4-25176 discloses a technique to prevent leakage of B in a p-channel MOSFET. According to the publication, the gate electrode is composed of poly-crystal Si containing impurities such as Ge (germanium), and is doped by implanting B, which is effective in suppressing growth of grains of the poly-crystal Si in a heating process, and preventing B from diffusing along the grains. However, an existing gate electrode is usually provided with a silicide electrode which is formed thereon through silicidation, in order to accomplish low resistivity. The silicide electrode containing impurities such as Ge of the gate electrode suffers from a high resisisity. Therefore, it is very difficult to accelerate a switching operation of the MOSFET and reduce a power supply voltage.
(4) In the elevated electrode, B is used as the p-type impurity in order to form the source and drain electrodes of the p-channel MOSFET. B diffuses faster than As as the n-type impurity. Therefore, sufficient shallowing cannot be accomplished in the p-channel MOSFET, which prevents high integration of the semiconductor integrated circuit.
(5) Further, since B in the elevated electrode cannot have sufficiently high active concentration, the elevated electrode suffers from high resistivity. Therefore, it is very difficult to accelerate the switching operation of the p-channel MOSFET and reduce a power supply voltage.
(6) Research and development have in progress in order to form a silicide electrode in the elevated electrode and accomplish low resistivity in the elevated electrode. However, since it is impossible to minimize a contact resistance between the elevated electrode and the silicide electrode, it has been impossible to accelerate the switching operation of the MOSFET and reduce a power supply voltage.
SUMMARY OF THE INVENTION
This invention has been contemplated in order to overcome the foregoing problems of the related art. A first object of the invention is to provide a semiconductor integrated circuit including an insulated gate field effect transistor (IGFET) in which a gate electrode of the IGFET is protected against leakage of a doped impurity to a channel region in order to accomplish a reliable threshold voltage and improve elec
Aoki Nobutoshi
Mizushima Ichiro
Ohuchi Kazuya
Foley & Lardner
Kabushiki Kaisha Toshiba
Rao Shrinivas H.
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