Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-02-18
2004-06-01
Whitmore, Stacy A. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06745375
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This application relates to functional verification operations, and more particularly to race condition ordering systems and methods used in functional verification modeling.
2. Description of Related Art
Pre-silicon verification operations consume as much as 50% of the total design time for system-on-a-chip projects. Such design verification includes simulation in a hardware description language (HDL) and comparison of the simulation results with functional model design results based upon the same stimulus. A race condition in HDL simulation includes one or more signals changing in the same time slice, when an operation depends on the order of occurrence of particular signal changes. As a result, HDL simulation does not guarantee an identical evaluation under race conditions. In HDL design descriptions, race conditions in a design need to be methodically planned for and avoided, to ensure hardware operation upon design implementation. In HDL simulators, the order of operations is not specified as to race conditions. However, in constructing functional models for verification, dealing with race conditions is unavoidable. For example, it may be necessary to compare an HDL code block output with results derived from certain inputs. Early during design, simulations are run without considering timing delays. Further, the inputs and outputs of a block may be propagated for functional verification during the same time slice. This presents an undesired race condition under which it is unclear which information will first be used, which detrimentally affects the results of verification, because depending upon the order of arrival of simulation events at a functional verification model, false failures are detectable. According to one current approach, complex semaphores are employed to ensure operability in the face of race conditions. Such complex solutions are dependent upon particular race conditions, and the design of the software code for the solutions is time-consuming and inefficient. Further, the use of semaphores creates ambiguities which detrimentally affect maintenance and reusability of the functional model.
It is desirable that solutions be developed which limit computational overhead to a minimum and which require a minimum memory allocation.
SUMMARY OF THE INVENTION
According to the present invention, an event sequencer for a functional mechanism contains a list of signatures and corresponding priority designations, and an event list containing event information including race condition events that are to be re-ordered. A method for sequencing race condition events according to the present invention, includes storing signatures for identifying predetermined events, storing priority designations corresponding to the signatures to enable identification of relative priorities between identified events, detecting at least first and second potential race condition events and information about each event, storing the events and event information associated with each event, sorting the events, and sending the sorted events to a functional mechanism. Events are compared with stored signatures, and signature matches are determined to determine whether an actual race condition exists. The arrival of events is detected, events are compared with stored signatures, and matches between events and signatures are established. Events are handled by detecting their arrival and making a determination as to whether to enter into a new time slice. Additionally, the events within each time slice are reordered by the sequencer according to the present invention. Finally, the sequencer sends the reordered, stored events to the functional model in a playback mode, according to the present invention.
Further according to the present invention, the computational load in using a sequencer system is kept to a minimum, as are the memory allocation requirements demanded for sequencer operation. Thus, functional models that do not require the services of a sequencer do not carry the computational overhead introduced by the sequencer, nor do they require the additional allocation of memory resources which a sequencer would require. According to the present invention, functional models that do not require sequencing are created with the same framework as functional models that do require sequencing, while eliminating the sequencer's computational overhead for functional models that do not require sequencing, and allowing functional models that to not require sequencing to be created without allocating the memory required to support the sequencer. Further, both sequenced and un-sequenced functional models coexist according to the present invention in the same sequenced verification framework, permitting the un-sequenced functional models to avoid the computational and memory allocation overhead incurred by the sequencer.
REFERENCES:
patent: 6053947 (2000-04-01), Parson
patent: 6074426 (2000-06-01), Baumgartner et al.
patent: 6097885 (2000-08-01), Rayner
Cirrus Logic Inc.
Lin, Esq. Steven
Whitmore Stacy A.
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