Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2002-11-12
2004-11-09
Yoha, Connie C. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S202000, C365S189080, C365S185250
Reexamination Certificate
active
06816421
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-265773, filed Sep. 11, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory, particularly relates to a semiconductor memory having a hierarchical bit line structure, for example, a semiconductor memory for use in a NOR type flash memory.
2. Description of the Related Art
There is a NOR type flash memory as one of the nonvolatile semiconductor memories.
FIG. 9
is an equivalent circuit diagram showing a part of a memory cell array in the NOR type flash memory.
Memory cell transistors (hereinafter referred to as “cell transistor”) are arrayed in a matrix form on a semiconductor substrate, control gates of the cell transistors are connected to corresponding word lines WL
0
to WLn. Bit lines BL
0
to BLm are provided on a CVD oxide film of the semiconductor substrate where the cell transistors are formed. Drains of the cell transistor are connected to corresponding bit lines BL
0
to BLm.
FIG. 10
shows a sectional view of the cell transistor in FIG.
9
. The cell transistor has a MOSFET structure in which a floating gate is formed on the semiconductor substrate through a tunnel oxide film and the control gate is formed on the floating gate through an inter-gate insulating film. A threshold voltage of the cell transistor is varied by the number of electrons stored in the floating gate.
FIG. 11
shows a relationship between a control gate voltage and a drain current of the cell transistor shown in FIG.
10
.
A state in which the relatively many electrons are stored in the floating gate and the threshold voltage Vt of the cell transistor is high is defined as “0” data. On the contrary, a state in which the relatively few electrons are stored in the floating gate and the threshold voltage Vt is low is defined as “1” data.
Voltage applied to the control gate of the cell transistor (word line voltage) is varied by operating modes. Table 1 shows an example of bias conditions of data read, data write, and data erase for the cell transistor. Where Vg is a control gate voltage, Vd is a drain voltage, and Vs is a source voltage.
TABLE 1
(Read)
(Program)
(Erase)
Vg
5 V
9 V
−7 V
Vd
1 V
5 V(“0”),
Floating
0 V(“1”)
Vs
0 V
0 V
10 V
As shown in Table 1, in case of the read of data, a voltage of 0V is applied to the source, a voltage of 1V is applied to the drain (bit line connected to cell transistor), a read voltage of 5V is applied to the control gate to determine whether or not a predetermined cell current is flown.
The write of data is carried out for every bit. In the write of data, the voltage of 0V is applied to the source and the voltage of 9V is applied to the control gate. In case that the “0” data is written, the voltage of 5V is applied to the drain so that the high energy electron generated by a channel hot electron phenomenon is injected to the floating gate, which causes the threshold voltage Vt to be changed. When the “1” data is held, the voltage of 0V is applied to the drain so that the injection of the electron to the floating gate is not occurred, and thus the change in the threshold voltage Vt is not occurred.
The erase of data is carried out collectively to the plurality of cell transistor having the source and the P-well in common. In the erase of data, the voltage of 10V is applied to the source, an erase voltage of −7V is applied to the floating gate, and the drain is set to be a floating state. As a result, the electron is flown from the floating gate to the substrate by an F-N tunnel phenomenon, all the target cell transistors for erasing are set to be the “1” data.
In order to confirm the write and the erase of data to the cell transistors, write verify and erase verify are carried out.
In the write verify, the read of “0” is carried out in a manner that the higher voltage Vpv compared with the voltage in reading is applied to the control gate of the cell transistor. The write and the write verify are carried one after the other, and then the write operation is ended when all the target cell transistors for writing are set to be “0”.
In the erase verify, the read of “1” is carried out in a manner that the lower voltage Vev compared with the voltage in reading is applied to the control gate of the cell transistor. The erase and the erase verify are carried one after the other, and then the erase operation is ended when a cell current Icell of the target cell transistor for erasing is secured sufficiently (when all the target cell transistors for erasing are set to be “1”).
FIG. 12
shows a part of the conventional NOR type flash memory in which a memory core portion has the hierarchical bit line structure.
In
FIG. 12
, reference numeral
1
is a cell transistor area,
2
is a lower column gate area,
3
is a cell block,
4
is a column reset transistor area, and
5
is an upper column gate area.
That is to say, the memory cell array having cell transistor QC arrayed in a matrix form is divided into the plurality of cell blocks
3
in a longitudinal direction (i.e. column direction) of the upper bit lines MBL
0
, MBL
1
, . . . . The upper bit lines MBL
0
, MBL
1
, . . . are common for the plurality of cell blocks
3
a.
Operation such as the read and the write is carried out while selecting one of the plurality of cell blocks
3
.
In each cell block
3
, a plurality of lower bit lines BiBL
0
, BiBL
1
, BiBL
2
, BiBL
3
, . . . (i=0, 1, . . . ) are provided to extend in the column direction of the memory cell array. Drains of a plurality of cell transistors QC are connected to a corresponding one of the lower bit lines BiBL
0
, BiBL
1
, BiBL
2
, BiBL
3
, . . . . Also in each cell block
3
, a plurality of word lines BiWL
0
, BiWL
1
, BiBL
2
, . . . (i=0, 1, . . . ) are provided to extend in a row direction of the memory cell array. Control gates of a plurality of cell transistors QC are connected to a corresponding one of the word lines BIWL
0
, BiWL
1
, BiBL
2
, . . . . Adjacent two lower bit lines (BiBL
0
, BiBL
1
), (BiBL
2
, BiBL
3
), . . . of the lower bit lines BiBL
0
, BiBL
1
, BiBL
2
, BiBL
3
, . . . form one pair. The adjacent two lower bit lines (BiBL
0
, BiBL
1
), (BiBL
2
, BiBL
3
), . . . are commonly connected to a corresponding one of the upper bit lines MLB
0
, MLB
1
, . . . through respective column selection transistors (lower column gates) QLCG. Each of the column selection transistors QLCG is controlled by a signal of a corresponding one of column selection lines BiH
0
, BiH
1
, . . . (i=0, 1, . . . ). The lower bit lines BiBL
0
, BiBL
1
, BiBL
2
, BiBL
3
, . . . comprise metal wirings of a first-stage layer and the upper bit lines MBL
0
, MBL
1
, . . . comprise metal wirings of a second-stage layer.
In each cell block
3
, a drain of a column reset transistor QCRT is connected to upper bit lines MBL
0
, MBL
1
, . . . . In the column reset transistor QCRT, a source of the column reset transistor QCRT is connected to a reset voltage line VRSTi (i=0, 1, . . . ), and a gate of the column reset transistor QCRT is connected to a column reset line COLRSTi (i=0, 1, . . . ).
Each of the upper bit lines MBL
0
, MBL
1
, . . . is connected to a data line DL and a sense amplifier
15
through a corresponding one of upper bit line selection transistors (upper column gates) QUCG. Upper column selection lines XiD
0
, XiD
1
, . . . (i=0, 1, . . . ) are connected to the gates of the respective upper bit line selection transistors QUCG.
As described later, the column reset transistor QCRT functions to reset charges of bit lines after read operation and also apply a stress voltage to the drain of the cell transistor through bit lines in the drain stress test (bit line test), so that the column reset transistor QCRT is a column-resetting and bit line testing transistor.
FIG. 15
is an example of a circ
Tanzawa Toru
Umezawa Akira
Kabushiki Kaisha Toshiba
Yoha Connie C.
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