Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2001-09-29
2004-08-17
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S105000, C713S401000, C713S500000
Reexamination Certificate
active
06779096
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This application relates generally to the fields of computer architecture and calibration and more specifically to tuning of performance parameters within a system based on characteristics of an individual system.
2. Description of the Related Art
Timing in modern computer systems is typically set with the worst-case timing margins for a set of components and the overall design as the starting point. Thus, even systems that have fast components and light bus loading may have timing parameters which are appropriate for systems with significantly different and significantly more components. In the case of some computers, timing parameters are set such that the timing will work in situations where extra components are added to the system, even though some such systems may never have the extra components in question.
By choosing the worst-case timing parameters, every system may be expected to operate as specified, but no system will take advantage of conditions allowing for enhanced performance. Timing parameters such as clock offsets may be set based on worst-case setup and hold times, even though a single component may not possibly have both a worst-case setup time and a worst-case hold time. Thus, it may be advantageous to allow for calibration or setting of time parameters based on an evaluation of components in a system at the time the system is running.
SUMMARY OF THE INVENTION
In one embodiment, the invention is an apparatus. The apparatus includes a first subsystem and a second subsystem coupled to the first subsystem. The apparatus also includes a clock signal generator coupled to the first subsystem and coupled to the second subsystem. The clock signal generator is to supply a first clock to the first subsystem and to supply a second clock to the first subsystem and to supply a third clock to the second subsystem. Each of the first clock, the second clock and the third clock are derived from a common clock, the first clock having a first predetermined phase offset relative to the third clock, and the second clock having a second predetermined phase offset relative to the third clock. The first predetermined phase offset and the second predetermined phase offset are adjustable based on performance characteristics of the first subsystem and performance characteristics of the second subsystem.
REFERENCES:
patent: 3633174 (1972-01-01), Griffin
patent: 6026050 (2000-02-01), Baker et al.
patent: 6334174 (2001-12-01), Delp et al.
patent: 6553472 (2003-04-01), Yang et al.
patent: 6646953 (2003-11-01), Stark
patent: 2003/0084233 (2003-05-01), Williams
Cornelius William
Taoyama Minoru
Thompson Paul
Apple Computer Inc.
Nguyen Hiep T.
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