Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-12-27
2004-06-08
Myers, Paul R. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S311000, C710S313000, C710S315000, C710S008000, C710S010000, C710S016000
Reexamination Certificate
active
06748478
ABSTRACT:
BACKGROUND
1. Field
The subject matter disclosed herein relates to data busses. In particular, the subject matter disclosed herein relates to data busses for transmitting data among devices coupled to data busses.
2. Related Information
Processing platforms typically employ data busses for transmitting data between a host processor and peripheral devices coupled to the busses. Such a data bus typically has a limited number of connection points for coupling to devices, and can typically only directly couple to a finite number of peripheral devices. To expand the number of peripheral devices to communicate with a host processor, a bridge may be coupled to a connection point on a bus to form an additional bus.
Host processor based software typically executes an enumeration procedure to identify devices coupled to the data busses, and to allocate processing resources for facilitating communication with the coupled devices. Resources may be allocated to devices coupled to a data bus behind a bridge either “transparently” or “non-transparently.” In a transparent resource allocation procedure, the host processor typically identifies the devices behind the bridge and specifically allocates processing resources to the devices. In a non-transparent resource allocation, a host processor may allocate resources to the bridge without knowledge of the specific peripheral devices coupled to the host processor through the bridge.
A system board may be constructed to comprise a CPU, system memory and host bridge to connect to a data bus. The data bus function may be expanded by the use of a transparent bridge to couple the data bus to an external data bus. The system board may then be integrated with a processing platform by coupling the transparent bridge to the data bus. The implementation of transparent or non-transparent resource allocation has typically involved the use of different devices for implementing transparent and non-transparent bridges. Therefore, manufacturing some system boards employing transparent bridge devices and other system boards employing non-transparent bridge devices, as well as differentiating among underlying system board designs, depends upon whether transparent or non-transparent resource allocation is to be employed.
REFERENCES:
patent: 5734850 (1998-03-01), Kenny et al.
patent: 5832238 (1998-11-01), Helms
patent: 6295566 (2001-09-01), Stufflebeam
patent: 6425033 (2002-07-01), Conway et al.
patent: 6574695 (2003-06-01), Mott et al.
patent: 6606679 (2003-08-01), Solomon et al.
patent: 6665762 (2003-12-01), Hofer
PCI Local Bus, PCI-to-PCI Bridge Architecture Specification, 149 pages.
21555 Non Transparent PCI-to-PCI Bridge, Advanced Information User's Manual, 204 pages.
CompactPCI® Specification, PICMG 2.0 R3.0, Oct. 1, 1999 (including ECN 2.0-3.0-002: Self-Describing Slot Geography Adopted Jan. 23, 2002)—PCI Industrial Computers.
Burke Brian M.
Campbell Matthew C.
Finamore Nicolas
Solomon Gary A.
Theall Matthew D.
Nagy Paul G.
Phan Raymond N
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