Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-08-26
2004-06-29
Niebling, John F. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S919000, C438S454000, C257S368000, C257S630000
Reexamination Certificate
active
06756619
ABSTRACT:
TECHNICAL FIELD
The invention pertains to semiconductor constructions and methods of forming semiconductor constructions. In particular aspects, the invention pertains to methods of forming DRAM constructions.
BACKGROUND OF THE INVENTION
Electrical isolation is commonly utilized in semiconductor constructions to alleviate, or prevent, leakage between electrical devices. For instance, it is frequently desired in dynamic random access memory (DRAM) fabrication to avoid sub-threshold leakage between access devices (such as, for example, access transistor constructions). There can be several facets which influence leakage currents between field effect transistor devices, including, for example, junction leakage in source/drain regions; drain-induced barrier lowering (DIBL) due to short gate lengths; gate-induced drain leakage (GIDL) due to high electric fields in a gate overlap region; narrow-width effects; and stress-induced leakage current (SILC) due to a proximity of an isolation region to a device.
A ratio of I
on
(drive current) to I
off
(sub-threshold leakage) can be utilized as a figure of merit for determining if access devices are performing adequately. It is found that reducing gate oxide thickness of access devices can improve a sub-threshold behavior of the devices while simultaneously increasing a drive current. However, a threshold voltage of a device reduces with the decrease in gate oxide thickness. Increasing dopant levels in channels of the devices can increase the threshold voltage to an acceptable level and compensate for the reduction in gate oxide thickness, but can increase junction leakage in source/drain regions. Additionally, the increased dopant level in a channel of a device can adversely cause junction capacitance to increase, cause channel mobility reduction, and reduce the current drive of the device.
It would be desirable to develop new methods for reducing sub-threshold leakage of devices. It would be further desirable if such new methods avoided increasing dopant concentration in channel regions of access devices. Additionally, it would be desirable if such new methods could be utilized for forming structures suitable for electrical isolation in an integrated circuit construction.
SUMMARY OF THE INVENTION
In one aspect, the invention encompasses a semiconductor construction having a pair of channel regions within a semiconductor substrate. Each of the channel regions has a sub-region which is doped with indium or heavy atom acceptor atoms such as Ga or Tl. The channel also contains boron surrounding the sub-region. A pair of transistor constructions is disposed over the semiconductor substrate, each of the transistor constructions is disposed over one of the channel regions. The pair of transistor constructions is separated by an isolation region which isolates the transistor constructions from one another. Each transistor construction has a transistor gate that is substantially laterally centered over the corresponding channel region. Each of the gates is wider than the underlying indium doped sub-region.
In one aspect, the invention encompasses a semiconductor construction having a first and a second transistor construction over a semiconductive substrate material. Each of the first and second transistor constructions has opposing sidewalls and a pair of insulative spacers along the sidewalls. The first transistor construction is disposed between a first and a second source/drain region within the substrate. A first end of the first source/drain region extends beneath the spacer on a first side of the first transistor construction and the second source/drain region extends beneath the spacer on an opposing second side of the first transistor construction. The second transistor construction is disposed between a third and a fourth source/drain region within the substrate. A first side of the fourth source/drain region extends beneath the spacer on a first side of the second transistor construction. The third source/drain region extends beneath the spacer on an opposing second side of the second transistor construction. The first, second, third and fourth source/drain regions are commonly doped with a first type of dopant. A source/drain extension which is doped with a second type of dopant is associated with the first side of the first source/drain region and extends the first side of the first source/drain region farther beneath the first transistor construction. Source/drain extensions are absent from a second side of the first source/drain region and are also absent from the second source/drain region.
The invention also encompasses methods of forming semiconductor constructions.
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Kennedy Jennifer M.
Micro)n Technology, Inc.
Niebling John F.
Wells St. John P.S.
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