Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-15
2004-06-08
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S368000, C257S392000, C257S500000
Reexamination Certificate
active
06747309
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method of manufacturing an integrated semiconductor device comprising a nonvolatile floating gate memory and to the related integrated device. In particular, such a method will be integrable in logic processes of advanced generations.
BACKGROUND OF THE INVENTION
Due to the increasing complexity of integrated circuits, e.g. based on microcontrollers or DSP, it becomes necessary to use more and more complex programs, usually stored in a ROM (Read Only Memory) of the final device, and subject to variations during the development steps.
On the other side, the increase of the number of metal levels in the integrated circuits increases the cycle time for manufacturing the ROM memories with new contents, so that it is desirable to have an electrically programmable memory for storing programs during the product development steps.
Such a memory can be also used in the production version, both in case that some program releases have to be supported, and when the volumes are not excessive, if the added costs of the programmable memory are not excessive.
One of the possible solutions is the use of a Static RAM (SRAM) or a Dynamic RAM (DRAM), wherein the code is loaded from an external EPROM (Electrically Programmable Read Only Memory). Such a solution has the drawback of taking up a large silicon area, of requiring in all cases an external memory, of involving a high dissipation (in case of DRAM), and of requiring an extensive re-planning for the production version.
A possible different solution is the use of a conventional EPROM with two polysilicon levels, transformable then in a ROM in the production version. This solution is very efficient but requires a costly dedicated manufacturing process. Moreover, the manufacture of the EPROM can modify the logic process features.
A third solution is described in U.S. Pat. No. 5,395,778 in name of Philips, wherein an OTP (One Time Programmable) memory based on the same programming mechanism of EPROMs is used, but it is cheaper. This solution seems optimal for 0.5 &mgr;m processes.
The utilization of a low cost OTP memory as described in U.S. Pat. No. 5,395,778 is based on some essential features: the memory cell oxide is the same oxide used also for the logic circuitry; the process steps dedicated for manufacturing high voltage transistors are not present.
However, these features cause problems when it is desired to transfer this memory architecture to more advanced CMOS processes. Particularly, the gate oxide thickness continues to decrease with the subsequent process generations. For example, there is a passage from 0.5 &mgr;m process generations with gate oxide thickness of 10-12 &mgr;m to 0.25 &mgr;m process generations with thickness of 4-5 nm to 0.15 &mgr;m process generations with gate oxide thickness of 2-3 nm.
However, there is a critical limit for the gate oxide thickness that can be used in a nonvolatile memory, due to the tunnel effect directed through the gate oxide, that makes it difficult to keep the charge stored in the floating gate. This limit occurs at a gate oxide thickness of about 5 nm.
A further problem present in U.S. Pat. No. 5,395,778 is connected to the programming voltage management. In fact, the voltages necessary for programming do not scale down as does the process generation. Thus, during the programming step, it is necessary to operate with voltages higher than that usually utilized in the circuit. Also in this case the problems increase passing to more advanced CMOS generations. For example, while the 12 nm oxide, used for the 0.5 &mgr;m generation, can support for short periods a voltage of 10 V necessary for programming step, the 7 nm oxide, required by 0.35 &mgr;m processes, can support only a maximum voltage value of about 5.5 V. For controlling the programming voltages that in this particular generation decrease up to 8.0-8.5 V, complex circuit configurations have to be used. The problem is more critical for 0.25 &mgr;m processes, wherein the difference between the maximum voltage supportable by the gate oxide (3.5 V) and the programming voltage (7-8 V) is greater.
The architecture proposed in U.S. Pat. No. 5,395,778 is incompatible with an extension to advanced CMOS processes.
SUMMARY OF THE INVENTION
In view of the state of the art described, the invention provides a method of manufacturing a low cost OTP memory.
According to the present invention, a method of manufacturing an integrated semiconductor device comprising at least one non-volatile floating gate memory cell and at least one logic transistor is provided. The method comprises a first step of growing a first gate oxide layer over a silicon substrate, a second step of depositing a first polysilicon layer over said first gate oxide layer, a third step of selectively etching and removing said first polysilicon layer in order to define the floating gate of said memory cell, a fourth step of introducing dopant in order to obtain source and drain regions of said memory cell, a fifth step of depositing a dielectric layer, a sixth step of selectively etching and removing said dielectric layer and said first polysilicon layer in a region wherein said logic transistor will be formed, a seventh step of depositing a second polysilicon layer, an eighth step of selectively etching and removing said second polysilicon layer in order to define the gate of said logic transistor and the control gate of said memory cell. Between said sixth step and said seventh step there is a first sub-step of removing said first gate oxide layer in said region for said logic transistor, a second sub-step of growing a second oxide gate layer over said region, said second gate oxide layer being different from said first gate oxide layer.
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Alfonso Maurelli
Baldi Livio
Jorgenson Lisa K.
Prenty Mark V.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
Tarleton E. Russell
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