Methods for improving within-wafer uniformity of gate oxide

Details Methods for improving within-wafer uniformity of gate oxide Methods for improving within-wafer uniformity of gate oxide

2002-08-07

2004-08-24

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

C438S761000

Reexamination Certificate

active

06780788

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to processes for forming gate oxides on semiconductor wafer substrates. More particularly, the present invention relates to methods for improving the within-wafer thickness uniformity of a gate oxide layer on a semiconductor wafer.
BACKGROUND OF THE INVENTION
In the semiconductor fabrication industry, silicon oxide (SiO
2
) is frequently used for its insulating properties as a gate oxide or dielectric. As the dimensions of device circuits on substrates become increasingly smaller, the gate dielectric thickness must decrease proportionately in field effect transistors (FETs) to approximately 3 to 3.5 nonometers. Accordingly, device performance and reliability can be adversely affected by such factors as interfacial defects, defect precursors and diffusion of dopants through gate dielectrics, as well as unintended variations in thickness in the gate oxide layer among central and peripheral regions of the layer.
A current drive in the semiconductor device industry is to produce semiconductors having an increasingly large density of integrated circuits which are ever-decreasing in size. These goals are achieved by scaling down the size of the circuit features in both the lateral and vertical dimensions. Vertical downscaling requires that the thickness of gate oxides on the wafer be reduced by a degree which corresponds to shrinkage of the circuit features in the lateral dimension. While there are still circumstances in which thicker gate dielectrics on a wafer are useful, such as to maintain operating voltage compatibility between the device circuits manufactured on a wafer and the current packaged integrated circuits which operate at a standard voltage, ultrathin gate dielectrics will become increasingly essential for the fabrication of semiconductor integrated circuits in the burgeoning small/fast device technology.
Because it is strongly correlated with gate oxide integrity, uniformity in thickness among all regions of the gate oxide layer is a major challenge and concern in ultrathin gate oxide fabrication. In a conventional oxidation process, wafers are heated in a furnace using heat furnished by a heater positioned outside the furnace. As a result, the wafers are heated from the edge to the center of the wafer, and the temperature of the wafer edge is thus always higher than the temperature at the wafer center. Hence, the oxidation rate is higher at the wafer edge than at the wafer center, and this temperature disparity is the main cause of oxide thickness non-uniformity within the wafer. This effect is illustrated in
FIG. 1
, which indicates the relative gate oxide thickness between the peripheral or edge region
12
of a semiconductor wafer
10
and the center region
14
of the wafer
10
after a gate oxide deposition process. In
FIG. 1
, the mottled appearance indicates areas of greater oxidation thickness in the peripheral region
12
of the wafer
10
relative to the lower oxidation thickness indicated by the non-mottled appearance in the more central region
14
of the wafer
10
. This disparity in oxide thickness between peripheral and central regions of the wafer may be as large as two angstroms, is typical of results obtained after using both horizontal and vertical type furnaces, and is exacerbated as the size of the wafer increases from 200 mm to 300 mm. As oxide thickness scales down to direct-tunneling regime (i.e., Tox<3 nm), this effect renders the process control non-tolerable.
Plasma nitridation is a new and promising technique used to improve oxide reliability as well as reduce gate leakage current. U.S. Pat. No. 6,225,169 details a method of constructing a gate dielectric on a semiconductor surface including cleaning a silicon surface then growing a silicon nitride barrier layer on the silicon surface using a high density plasma (HDP) of nitrogen. A gate dielectric layer is then deposited on the silicon nitride layer and a second silicon nitride layer is then grown on the dielectric layer, also using an HDP nitrogen plasma, followed by deposition of the conductive gate layer. The HDP nitrogen plasma is heated using an inductively coupled ratio frequency generator. The invention also includes a gated device including a gate dielectric constructed on a semiconductor surface by the method of the invention.
U.S. Pat. No. 6,110,842 describes a method for forming integrated circuits having multiple gate oxide thicknesses. A high density plasma is used for selective plasma nitridation to reduce the effective gate dielectric thickness in selected areas only. In one embodiment, a pattern is formed over a substrate and a high density plasma nitridation is used to form a thin nitride or oxynitride layer on the surface of the substrate. The pattern is removed and oxidation takes place. The nitride or oxynitride layer retards oxidation, whereas in the areas where the nitride or oxynitride layer is not present, oxidation is not retarded. In another embodiment, a thermal oxide is grown. A pattern is then placed that exposes areas where a thinner effective gate oxide is desired. The high density plasma nitridation is performed converting a portion of the gate oxide to nitride or oxynitride. The effective thickness of the combined gate dielectric is reduced.
SUMMARY OF THE INVENTION
The present invention includes two novel methods for improving gate oxide uniformity and reliability in ultrathin gate oxide processing. Both approaches take advantage of plasma nitridation, an effective treatment to incorporate nitrogen into ultrathin oxide for leakage current and EOT reduction. It is well-known that furnace oxidation results in an edge-thick oxidation profile due to heating of the wafer from edge to center. According to a first embodiment of the present invention, a gate oxide layer is formed on a wafer substrate using a conventional oxidizing process typically in a batch-type furnace. The resulting edge-thick oxidized wafer is then nitridized using a plasma nitridation process. By intentionally tuning the nitridation profile as center-thick, final within-wafer uniformity can be vastly improved.
According to a second embodiment of the present invention, the wafer surface is first nitridized by plasma nitridation and then oxidized to form the gate oxide in an oxidation furnace. As in the Nitrogen-Implanted Silicon Substrate (NISS) technique, nitrogen is incorporated into the gate oxide, thereby reducing the oxidation rate. By intentionally incorporating a higher quantity of nitrogen into the wafer edge, the oxidation rate at the wafer edge can be suppressed and compensate for the edge-thick characteristic normally resulting from furnace oxidation. The methods of the present invention are particularly beneficial in the formation of uniform gate oxides on 300 mm wafers, since it is conventionally more difficult to control within-wafer uniformity of ultrathin oxides on 300 mm wafers.
An object of the present invention is to provide novel methods for improving within-wafer uniformity of a gate oxide on a substrate.
Another object of the present invention is to provide novel methods for improving the integrity of a gate oxide layer on a substrate.
Still another object of the present invention is to provide novel methods which compensate for edge-thick oxidation of semiconductor wafers due to non-uniform heating of the wafers in the gate oxidation process.
Yet another object of the present invention is to provide novel methods which utilize plasma nitridation to improve within-wafer uniformity of a gate oxide layer on a semiconductor wafer substrate.
A still further object of the present invention is to provide a method including formation of a gate oxide layer on a wafer substrate followed by nitridation of the gate oxide layer to compensate for an edge-thick oxide gate profile obtained during the oxidation process.
Still another object of the present invention is to provide a novel method in which plasma nitridation is used to intentionally tune a center-thick nitridation profile to compensate for an edge-thick gate oxide

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