Semiconductor memory device having multi-bit testing function

Details Semiconductor memory device having multi-bit testing function Semiconductor memory device having multi-bit testing function

2002-11-12

2004-11-09

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S042000, C365S189070, C365S189080, C365S233100

Reexamination Certificate

active

06816422

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a multi-bit testing function.
2. Description of the Background Art
In a semiconductor memory device wafer test, a multi-bit test is performed so as to increase the number of wafers which can be tested by one tester. In this multi-bit test, a plurality of bits are degenerated to thereby decrease the number of input/output terminals employed in the test. In case of a semiconductor memory device which functions as a word organization of “×16”, for example, four bits are degenerated to one bit by using a multi-bit test and a test data write/read test is performed to four input/output terminals, whereby a test can be performed to all memory cells.
The numbers of drivers and comparator pins to be provided in a tester employed for a test are determined according to the specification of the tester. Therefore, if the number of input/output terminals necessary to measure one device using a multi-bit test decreases, it is possible to increase the number of devices which can be simultaneously measured and to thereby enhance testing efficiency.
FIG. 24
is a functional block diagram for functionally describing data-read-related sections of a conventional semiconductor memory device which has a multi-bit testing function. It is noted that
FIG. 24
typically shows only important sections related to data output in the semiconductor memory device.
Referring to
FIG. 24
, the semiconductor memory device includes a memory cell array MA
100
which stores data, sense amplifiers SA
100
to SA
103
which detect data read from memory cell array MA
100
to bit line pairs BL
100
to BL
103
, input/output control circuits
711
to
714
which amplify the data read from sense amplifiers SA
100
to SA
103
to I/O line pairs LIO
100
to LIO
103
, respectively, and switches S
101
to S
104
which selectively output the data received from input/output control circuits
711
to
714
in accordance with a multi-bit test mode signal TMBT whose logic level becomes H (logic high)-level in a multi-bit test mode, to data bus pairs NDB
0
to NDB
3
or TDB
0
to TDB
3
, respectively.
Input/output control circuits
711
to
714
include preamplifiers/read data bus drivers which amplify the data read to I/O line pairs LIO
100
to LIO
103
and which output the amplified data to switches S
101
to S
104
during data read, respectively, and write amplifiers/write buffers which output the data received from switches S
101
to S
104
to I/O line pairs LIO
100
to LIO
103
during data write, respectively. In addition, sense amplifiers SA
100
to SA
103
write the write data received from the write amplifiers/write buffers of input/output control circuits
711
to
714
through I/O line pairs LIO
100
to LIO
103
, to bit line pairs BL
100
to BL
103
, respectively.
The semiconductor memory device also includes data bus pairs NDB
0
to NDB
3
which are connected to input/output control circuits
711
to
714
through switches S
101
to S
104
in a normal operation other than the multi-bit test mode (which normal operation will be referred to as “normal operation mode” opposed to the multi-bit test mode, hereinafter), and data bus pairs TDB
0
to TDB
3
which are connected to input/output control circuits
711
to
714
through switches S
101
to S
104
in the multi-bit test mode, respectively. Data bus pairs NDB
0
to NDB
3
are formed of data buses NDB
0
and /NDB
0
, data buses NDB
1
and /NDB
1
, data buses NDB
2
and /NDB
2
and data buses NDB
3
and /NDB
3
which transmit complementary data, respectively. Data bus pairs TDB
0
to TDB
3
is formed of data buses TDB
0
and /TDB
0
, data buses TDB
1
and /TDB
1
, TDB
2
and /TDB
2
and TDB
3
and /TDB
3
which transmit complementary data, respectively.
The semiconductor memory device further includes an I/O combiner
741
which degenerates and outputs the read data of four bits received from data bus pairs TDB
0
to TDB
3
, a data bus pair RTDB which transmit the data degenerated by the I/O combiner
741
, a read amplifier
721
which receives the data from data bus pair NDB
0
and that from RTDB, selects one of the data in accordance with multi-bit test mode signal TMBT, amplifies the signal level of the selected data and outputs the data to a data bus pair RDAMP
0
, read amplifiers
722
to
724
which receives the data from data bus pairs NDB
1
to NDB
3
, amplifies the signal levels of the data and outputs the data to data bus pairs RDAMP
1
to RDAMP
3
, respectively, and output circuits
731
to
734
which receive the data outputted from read amplifiers
721
to
724
and output the data to the outside of the semiconductor memory device, respectively. Data bus pair RTDB is formed of data buses RTDB and /RTDB which transmit complementary data.
In a multi-bit test for this semiconductor memory device, before reading data from memory cell array MA
100
, data at the same logic level are written to the corresponding memory cells of memory cell array MA
100
. In a multi-bit test mode, the logic level of multi-bit test mode signal TMBT becomes H level and switches S
101
to S
104
connect input/output control circuits
711
to
714
to data bus pairs TDB
0
to TDB
3
, respectively.
I/O combiner
741
degenerates the data of four bits received from data bus pairs TDB
0
to TDB
3
. Namely, if the data of four bits received from data bus pairs TDB
0
to TDB
3
are all at the same logic level, it is determined that data write and read have been normally performed and H-level data and L (logic low)-level data are outputted to data bus pair RTDB and /RTDB, respectively. If the data of four bits are not at the same logic level, it is determined that data write and read have not been normally performed and H-level data is outputted to each of data bus pair RTDB and /RTDB.
In the multi-bit test mode, only read amplifier
721
is activated among read amplifiers
721
to
724
. If the data received from data bus pair RTDB and /RTDB are at H level and L level, respectively, read amplifier
721
determines that data write and read have been normally performed and outputs an H-level signal to output circuit
731
. If the data received from data bus pair RTDB and /RTDB are both at H level, read amplifier
721
determines that data write and read have not been normally performed and outputs an L-level signal to output circuit
731
. Output circuit
731
outputs the received data to the outside of the semiconductor memory device. Other signals CKD, RDAI, /RDAI, RDAE and /RDAE received by read amplifiers
721
to
724
will be described later.
On the other hand, in a normal operation mode, the logic level of multi-bit test mode signal TMBT becomes L level and switches S
101
to S
104
connect input/output control circuits
711
to
714
to data bus pairs NDB
0
to NDB
3
, respectively. Read amplifiers
721
to
724
amplify the data read from memory cell array MA
100
to data bus pairs NDB
0
to NDB
3
and output the amplified data to output circuits
731
to
734
, respectively.
FIGS. 25 and 26
are circuit diagrams for describing the circuit configuration of read amplifier
721
. Referring to
FIG. 25
, read amplifier
721
includes an N-channel MOS transistor N
101
which is connected to data bus NDB
0
and a node RD and which has a gate receiving a signal /RDAI, an N-channel MOS transistor N
102
which is connected to data bus /NDB
0
and a node /RD and which has a gate receiving signal /RDAI, an N-channel MOS transistor N
103
which is connected to node RD and data bus RDAMP and which has a gate receiving signal /RDAE, and an N-channel MOS transistor N
104
which is connected to node /RD and data bus /RDAMP and which has a gate receiving signal /RDAE.
If signal /RDAI is at H level, N-channel MOS transistors N
101
and N
102
operate as an input circuit which takes in data on data bus pair NDB
0
and /NDB
0
into node pair RD and /RD. If signal /RDAE is at H level, N-channel MOS transistors N
103
and N
1

Affiliated with

Also associated with

Rating

Semiconductor memory device having multi-bit testing function does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having multi-bit testing function, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having multi-bit testing function will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3359351