Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-11-01
2004-06-22
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S623000, C257S757000, C257S758000, C257S760000
Reexamination Certificate
active
06753563
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of electronic devices, and more particularly to an integrated circuit having a doped porous dielectric and method of manufacturing the same.
BACKGROUND OF THE INVENTION
Integrated circuits typically contain a large number of semiconductor devices. Manufacturers of the integrated circuits often wish to decrease the size of the integrated circuits, which allows more circuitry to be placed within the same physical area of a circuit. To help decrease the size of the integrated circuits, the manufacturers may place the semiconductor devices closer together in the integrated circuits. One problem is that capacitance between the semiconductor devices typically increases as the space between the semiconductor devices decreases. The increased capacitance between the semiconductor devices can interfere with the operation of the semiconductor devices and with the operation of the integrated circuits.
One approach to decreasing the capacitance between the semiconductor devices involves decreasing the thickness of the semiconductor devices. For example, the manufacturers may reduce the thickness of gates used in transistors. The capacitance between the semiconductor devices is typically proportional to the cross-sectional area of the semiconductor devices. Because thinner semiconductor devices have less cross-sectional area, the capacitance between the semiconductor devices typically decreases. A problem with this approach is that difficulty may be encountered in maintaining the operation of the semiconductor devices. As the semiconductor devices become thinner, the reduced size of the devices may interfere with the ability of the devices to conduct. Eventually, the reduced thickness of the semiconductor devices may prevent the devices from conducting, and the semiconductor devices in the integrated circuits can fail.
Another approach to decreasing the capacitance between the semiconductor devices involves lowering the dielectric constant (K) of the insulating material between the devices. For example, oxide may be used as an insulating material in an integrated circuit, and oxide typically has a dielectric constant of approximately four. The capacitance between the semiconductor devices is typically proportional to the dielectric constant of the insulating material. As a result, lowering the dielectric constant of the insulating material reduces the capacitance between the semiconductor devices. A problem with this approach is that, as manufacturers place the semiconductor devices closer together, the dielectric constant of the insulating material may still be high enough to allow the formation of an appreciable amount of capacitance in the integrated circuit. Also, the insulating material may suffer from contamination, such as by metal ions like sodium, that interferes with the operation of the integrated circuit.
SUMMARY OF THE INVENTION
The present invention recognizes a need for an improved integrated circuit having a doped porous dielectric and method of manufacturing the same. The present invention reduces or eliminates at least some of the shortcomings of prior systems and methods.
In one embodiment of the invention, an integrated circuit includes a semiconductor device. The integrated circuit also includes a contact layer disposed outwardly from the semiconductor device and operable to provide electrical connection to the semiconductor device. In addition, the integrated circuit includes a dielectric layer disposed inwardly from the contact layer and outwardly from the semiconductor device. The dielectric layer comprises an at least substantially porous dielectric material doped with at least one dopant.
In a particular embodiment of the invention, the semiconductor device comprises a transistor. Also, the dielectric layer may, for example, include an at least substantially porous dielectric material doped with at least one of phosphorus, fluorine, carbon, and boron.
In another embodiment of the invention, a method for forming an integrated circuit having an at least substantially doped porous dielectric includes forming a semiconductor device. The semiconductor device comprises at least a portion of a semiconductor substrate. The method also includes forming a dielectric layer disposed outwardly from the semiconductor substrate and surrounding at least a portion of the semiconductor device. The dielectric layer comprises an at least substantially porous dielectric material doped with at least one dopant. In addition, the method includes forming a contact layer disposed outwardly from the dielectric layer and operable to provide electrical connection to the semiconductor device.
Numerous technical advantages can be gained through various embodiments of the invention. Various embodiments of the invention may exhibit none, some, or all of the following advantages. For example, in one embodiment of the invention, an integrated circuit is provided that uses a doped, at least substantially porous dielectric material disposed between a semiconductor device and a contact layer. The dielectric material may be doped with any suitable dopant material, such as phosphorus and fluorine. The use of a fluorine dopant decreases the dielectric constant of the dielectric material, which helps to reduce the capacitance between different conductive regions in the integrated circuit. The use of phosphorus reduces the effects of metallic contamination in the dielectric material, which helps to reduce or eliminate interference caused by the contaminant in the integrated circuit.
Another technical advantage of at least some embodiments of the invention is that the conductive regions in the semiconductor device retain an appropriate amount of thickness, helping to ensure that the integrated circuit operates properly. The conductive regions in the semiconductor device may retain enough thickness to conduct properly, which helps to ensure that the semiconductor device operates properly. The conductive regions need not be reduced in size to the point where it interferes with the ability of the integrated circuit to function.
Other technical advantages are readily apparent to one of skill in the art from the attached figures, description, and claims.
REFERENCES:
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patent: 6316833 (2001-11-01), Oda
Zielinski et al, “Damascene Integration of Copper and Ultra-Low-k Xerogel for High Performance Interconnects,” IEDM 97, pp. 936-938.
Lee et al., “Application of HSQ (Hydrogen Silsesquioxane) Based SOG to Pre-Metal Dielectric Planarization in STC (Stacked Capacitor) DRAM,” 1996 Symposium on VLSI Technology Digest of Technical Papers, pp. 112-113.
List et al, “Integration of Ultra-Low-k Xerogel Gapfill Dielectric for High Performance Sub-0.18 &mgr;m Interconnects,” 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 77-78.
Jeng, et al., “Process Integration and Manufacturability Issues for High Performance Multilevel Interconnect,” Mat. Res. Soc. Symp. Proc., vol. 337, pp. 25-31.
Brady III W. James
Garner Jacqueline J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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