Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-04-29
2004-11-30
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S304000
Reexamination Certificate
active
06825521
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semiconductor device having a capacitor and a method of manufacturing the same.
2. Description of the Prior Art
As one of the nonvolatile memories that can store information after the power supply is turned OFF, FeRAM (Ferroelectric Random Access Memory) having the ferroelectric substance is known. The FeRAM has such a structure that stores the information by utilizing the hysteresis characteristic of the ferroelectric substance, and can execute a high speed operation at a low power consumption. Thus, its future development is expected much more as the nonvolatile memory that can be rewritten so many times.
In the memory cell of the FeRAM, for example, there are 1T1C type that employs one transistor and one capacitor to store 1-bit information, and 2T2C type that employs two transistors and two capacitors to store 1-bit information. A cell area of the 1T1C type memory cell can reduce a cell area by half in comparison with the 2T2C type memory cell.
The capacitor of the memory cell of the FeRAM has such a structure that a plurality of upper electrodes are formed at an interval over a stripe-like lower electrode, which is called a cell plate, and the ferroelectric layer is put between the upper electrode and the lower electrode, for example. The cell plate serves as a common lower electrode of a plurality of capacitors. In this case, one upper electrode, the underlying ferroelectric layer, and the cell plate constitute one capacitor.
As the connection of the capacitors, it is set forth in Patent Application Publication (KOKAI) Hei 5-129156 that the capacitors are formed in series or in parallel by forming the upper electrodes or the lower electrodes of two capacitors commonly. More particularly, it is set forth in Patent Application Publication (KOKAI) Hei 5-129156 that two PZT ferroelectric films are formed on one lower electrode and then the upper electrodes are connected on these PZT ferroelectric films.
Meanwhile, if four upper electrodes or more are formed on one cell plate, they are formed in one column in the prior art. But they may be formed in two columns.
As the method of forming a plurality of upper electrodes on one cell plate in two columns, following steps are considered.
FIGS. 1A
to
1
D are plan views showing steps of forming the upper electrodes on one cell plate in two columns.
FIGS. 2A
to
2
D are sectional views showing steps of forming the upper electrodes on one cell plate in two columns, and are sectional views taken along a I—I line in FIG.
1
A.
First, as shown in FIG.
1
A and
FIG. 2A
, a first conductive film
102
, a ferroelectric film
103
, and a second conductive film
104
are sequentially formed on an interlayer insulating film
101
. Then, four upper electrodes
104
a
,
104
b
or more are formed in two columns along the cell plate forming region by patterning the second conductive film
104
while using a first resist pattern (not shown). Then, the resist is coated on the upper electrodes
104
a
,
104
b
and the ferroelectric film
103
, and then exposed/developed. Thus, a second resist pattern
105
is formed in the cell plate forming region except the cell plate contact area. In this case, side surfaces of two-column upper electrodes
104
a
,
104
b
, which are positioned on both sides of the cell plate forming region, are formed to coincide substantially with both side surfaces of the second resist pattern
105
.
Then, as shown in FIG.
1
B and
FIG. 2B
, the ferroelectric film
103
is etched by using the second resist pattern
105
as a mask. Then, the second resist pattern
105
is removed.
Then, as shown in FIG.
1
C and
FIG. 2C
, a resist is coated on the upper electrodes
104
a
,
104
b
, the ferroelectric film
103
, and the first conductive film
102
. Then, a third resist pattern
106
that covers selectively the overall cell plate forming region is formed by exposing/developing the resist.
Then, as shown in FIG.
1
D and
FIG. 2D
, a cell plate (lower electrode)
102
a
is formed by etching the first conductive film
102
while using the third resist pattern
106
as a mask. Then, the third resist pattern
106
is removed.
According to the above capacitor forming steps, if the second resist pattern
105
shown in FIG.
1
A and
FIG. 2A
is displaced from a desired position to either the right side or the left side, it is possible that, since one sides of the upper electrodes
104
a
,
104
b
aligned in two columns are etched when the ferroelectric film
103
is to be etched, an area of the left upper electrode
104
a
differs from an area of the right upper electrode
104
b
. Similarly, if the third resist pattern
106
shown in FIG.
1
C and
FIG. 2C
is displaced to any one of the left side and the right side, it is possible that the area of the left upper electrode
104
a
is different from the area of the right upper electrode
104
b.
The variation in the areas of the upper electrodes
104
a
,
104
b
acts as a cause to make capacitances of a plurality of capacitors in the memory cell region uneven, which exerts an influence upon the device operating margin. In particular, in the 1T1C type FeRAM, because “1” and “0” are read by comparing the capacitor of the memory cell with the reference capacitor, such variation in individual capacitor characteristics presents a serious problem.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device capable of reducing variation in an area of a plurality of upper electrodes that are formed in plural columns over a cell plate line, and a method of manufacturing the same.
According to one aspect of the present invention, there is provided a semiconductor device comprising: a first insulating layer formed over a semiconductor substrate; a cell plate line formed on the first insulating layer and having a slit that divides a region except a contact area into both sides; a capacitor dielectric layer formed on the cell plate line on both sides of the slit and having a clearance over the slit; and a plurality of capacitor upper electrodes formed on the capacitor dielectric layer in one column on both sides of the slit.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a first insulating layer over a semiconductor substrate; forming sequentially a first conductive layer, a dielectric layer, and a second conductive layer on the first insulating layer; forming a plurality of capacitor upper electrodes, which are aligned at an interval in plural columns, by patterning the second conductive layer; forming a first mask that has clearances between the capacitor upper electrodes in plural columns and passes over the plurality of capacitor upper electrodes in the plural columns respectively; forming a capacitor dielectric layer having clearances between the plural columns by etching the dielectric layer in a region that is not covered with the first mask; removing the first mask; forming a second mask, which has slits between the capacitor upper electrodes in the plural columns and is united by a contact area, on the capacitor upper electrodes, the capacitor dielectric layer, and the first conductive layer; forming a capacitor lower electrode, which has a contact area that is connected electrically to an external wiring, under the contact area by etching the first conductive layer in a region that is not covered with the second mask; and removing the second mask.
According to the present invention, the cell plate line in which the region (capacitor forming region) except the contact area to which the wiring or the plug is connected is divided into plural columns by the slit is provided, then the capacitor dielectric layer is formed in the region of the cell plate line on both sides of the slit respectively, and then a plurality of capacitor upper electrodes are formed in one column
Westerman Hattori Daniels & Adrian LLP
Wilson Allan R.
LandOfFree
Semiconductor device with capacitor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device with capacitor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device with capacitor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3358127