Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2002-06-14
2004-08-24
Leg, Eddie (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S766000, C257S778000, C257S777000
Reexamination Certificate
active
06781221
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a packaging substrate for electronic parts or elements such as semiconductor chips and to an electronic device having the packaged electronic elements. More particularly, the present invention relates to a packaging substrate designed to receive thereon electronic elements using different packaging methods, and an electronic device having the electronic elements packaged using such a packaging substrate.
2. Description of the Related Art
At present, a wide variety of packaging substrates are commercially available as substrates for packaging electronic parts such as semiconductor chips. Some packaging substrates are designed to receive on the same substrate different types of electronic parts such as semiconductor chips for a microprocessor and semiconductor chips for a memory. On these packaging substrates, the semiconductor chips are sometimes mounted with different packaging methods, that is, one type of semiconductor chip is mounted with a wire bonding method, and another type of semiconductor chip is mounted with a flip chip bonding method.
Generally, when a wire bonding method is used in the packaging of semiconductor chips on the packaging substrate, a bonding pad is formed on predetermined sites of a surface of the substrate. The bonding pad is generally produced by forming a wiring pattern from a wiring material such as copper (Cu), followed by forming on the wiring pattern a plating layer consisting of nickel (Ni) plating and gold (Au) plating. The plating layer is applied to improve the bonding strength between the bonding pad and the bonding wire.
On the other hand, when a flip chip bonding method is used in the packaging of semiconductor chips, a solder bump is generally applied to between a bonding pad of the packaging substrate and an external terminal or electrode of the semiconductor chips. Further, when the electrode of the semiconductor chips has a protruded electrode, comprising gold (Au) as a principal component thereof, on a tip position thereof, a solder material such as Sn—Pb or Sn—Ag is previously applied to the bonding pad of the substrate, and then the protruded Au electrode is bonded through the solder material to the bonding pad.
Thus, when the semiconductor chip designed for wire bonding and the semiconductor chip designed for flip chip bonding have to be mounted on the same packaging substrate, to avoid any problems caused due to packaging of two different semiconductor chips, bonding pads for the wire bonding and flip chip bonding were typically produced by forming wiring patterns from a suitable wiring material such as copper on the substrate. The wiring patterns were then plated with nickel and gold to form bonding pads which are suitable for wire bonding. Some of the thus obtained bonding pads were further coated with a soldering material to form solder-coated bonding pads suitable for flip chip bonding.
The above-described prior art method for forming the different bonding pads in the packaging substrate and the semiconductor device using the produced packaging substrate with the different bonding pads will be further described hereinafter with reference to
FIG. 1
showing the constitution of the prior art packaging substrate
11
having the area A designed to receive thereon an electronic element through wire bonding and the area B designed to receive thereon an electronic element through flip chip bonding,
FIG. 2
showing the construction of the electronic device, particularly semiconductor device
10
, using the packaging substrate of
FIG. 1
, and
FIGS. 3A and 3B
showing the constitution of the different bonding pads
12
and
55
used in the semiconductor device
10
of FIG.
2
.
As illustrated in
FIG. 2
, the semiconductor device
10
comprises a packaging substrate
11
and one main surface of the substrate
11
bears both of a semiconductor chip
20
for wire bonding and a semiconductor chip
30
for flip chip bonding, while another main surface of the substrate
11
opposed to the chips-bearing surface has a group of solder bumps
40
acting as an external connection terminal. The chip-bearing surface of the substrate
11
has formed thereon a wiring pattern
17
made of copper, and an insulating material
18
is further deposited except for the areas of the bonding pads
12
and
55
.
Referring to the area A of the packaging substrate
11
, there is illustrated the semiconductor chip
20
mounted on and bonded through an adhesion layer
21
to the substrate
11
, and its I/O terminal (not shown) is electrically connected through an Au bonding wire
22
to a bonding pad
12
. As shown in
FIG. 3A
, the bonding pad
12
is formed on the Cu wiring pattern
17
of the substrate
11
, and is constituted from a plating layer
14
formed by sequentially plating on a surface of the wiring pattern
17
a nickel plating
14
a
and a gold plating
14
b.
Referring to the area B of the packaging substrate
11
, there is illustrated the semiconductor chip
30
mounted through flip chip bonding to the substrate
11
. After positioning of the protruded electrode
32
of the semiconductor chip
30
to the bonding pad
55
formed on the wiring pattern
17
of the substrate
11
, the semiconductor chip
30
is bonded to the bonding pad
55
through a solder material
56
applied to a surface of the pad
55
. The protruded electrode
32
is generally formed in the form of an Au stud bump. As shown in
FIG. 3B
, the bonding pad
55
has a constitution similar to that of the bonding pad
12
except that its plating layer
14
consisting of a Ni plating
14
a
and an Au plating
14
b
further has a solder layer
56
to which the protruded electrode
32
is embedded for the bonding purpose. The space between the substrate
11
and the semiconductor chip
30
is filled with an electrically insulating under-filling resin
34
. Further, in the semiconductor device
10
, semiconductor chips
20
and
30
as well as other parts including the bonding wire
22
are covered and protected with an electrically insulating sealing resin
36
.
However, the prior art semiconductor devices such as those described above, referring to the attached drawings, suffer from important problems. The first problem is a problem caused in the bonding pad
55
for flip chip bonding due to diffusion of the gold from the Au plating
14
b
appearing on a surface of the bonding pad
55
to the solder layer
56
. Since an amount of the solder on the bonding pad
55
is low, a melting point of the solder layer
56
can be remarkably increased as a result of inclusion of the gold in the solder.
The problem of an increase in the melting point of the solder is particularly serious when the electrodes
32
are densely disposed on the semiconductor chip
30
, because a bonding surface of the bonding pads
55
is reduced with an increase of the distribution density of the electrodes
32
, and thus an amount of the solder to be applied to each bonding pad
55
is reduced. In other words, a ratio of the gold diffused in the solder is further increased, and as a result, the melting point of the solder is further increased.
In addition to the increase in the melting point of the solder, the melting point of the solder can be varied as a result of variation of the amount of the solder supplied to each bonding pad
55
. The variation of the amount of the solder is caused, because a pitch between the adjacent bonding pads
55
is narrowed in conformity with an increase in the distribution density of the electrodes
32
. As the melting point of the solder can be varied within about 50° C., it becomes difficult to ensure a reliable solder bonding between the semiconductor chip
30
and the substrate
11
.
Another problem arises due to the application of a solder to the bonding pad and other parts of the wiring pattern. For example, when a solder should be coated to the bonding pad, it is conventionally carried out to supply and print a solder paste at a predetermined pattern on the pad. However, when a pitch be
Leg Eddie
Owens Douglas W.
Shinko Electric Industries Co. Ltd.
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