Semiconductor device

Details Semiconductor device Semiconductor device

2001-01-05

2004-08-17

Nadav, Ori (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S371000, C257S377000, C438S521000, C438S529000

Reexamination Certificate

active

06777758

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to a technique of reducing the layout area of elements for fixing the potentials of wells in a semiconductor device.
2. Description of the Background Art
In a semiconductor integrated circuit, it is important to optimize the electric characteristics of individual elements and reduce the width of spaces between the elements, in order to improve the performance of and refine the integrated circuit. In general, a MOSFET is formed on a well prepared by doping a surface of a semiconductor substrate with an impurity. For example, an N-type MOSFET (hereinafter also referred to as “NMOSFET”) is formed on a P-type well (hereinafter also referred to as “P well”).
In this case, a plurality of types of NMOSFETs having different transistor characteristics can be formed on the same semiconductor substrate by adjusting only impurity profiles of portions close to surfaces of P wells or regions shallower than an element isolation insulator film (hereinafter also referred to as “element isolation film”). Alternatively, the characteristics of NMOSFETs formed on the same substrate can be made different from each other by adjusting impurity profiles of deeper regions, in order to optimize the electric characteristics of the elements. In other words, a plurality of types of P wells having different impurity profiles are prepared for forming NMOSFETs different in characteristic and application from each other on the P wells respectively.
FIG. 22
is a sectional view of a conventional semiconductor device
1
P, and
FIG. 23
is a typical plan view or layout diagram for illustrating a part of the semiconductor device
1
P. In the semiconductor device
1
P, P wells
11
P and
12
P having different impurity profiles are formed in a surface
50
SP of a semiconductor substrate (hereinafter also referred to as “substrate”)
50
P. In particular, an element isolation film
51
BP is formed at the boundary between the wells
11
P and
12
P in the conventional semiconductor device
1
P.
An NMOSFET
91
P is formed on the P well
11
P, and a P-type semiconductor layer (hereinafter also referred to as “P-type layer”)
21
P for fixing the potential of the P well
11
P is formed in the P well
11
P. Similarly, an NMOSFET
92
P different in characteristic from the aforementioned NMOSFET
91
P is formed on the P well
12
P, and a P-type layer
22
P for fixing the potential of the P well
12
P is formed in the P well
12
P. While the P-type layers
21
P and
22
P are formed in the vicinity of the boundary between the P wells
11
P and
12
P in
FIG. 22
, the P-type layers
21
P and
22
P may alternatively be formed on other portions in the P wells
11
P and
12
P respectively. Element isolation films
51
P and
51
BP isolate the NMOSFETs
91
P and
92
P and the P-type layers
21
P and
22
P from each other.
The P-type layers
21
P and
22
P are connected to a wire
40
P through contacts
31
P and
32
P provided in contact holes
70
H
1
P and
70
H
2
P formed in an interlayer isolation film
70
P respectively. The wire
40
P is connected to a prescribed potential, thereby fixing the P wells
11
P and
12
P to the prescribed potential through the contacts
31
P and
32
P and the P-type layers
21
P and
22
P.
Source/drain regions
61
P of the NMOSFETs
91
P and
92
P are formed in the surface
50
SP, and gate insulator films
63
P (see
FIG. 26
) and gate electrodes
62
P are successively formed on the surface
50
SP. The source/drain regions
61
P are connected to wires
66
P through contacts
65
P provided in contact holes
70
HP formed in the interlayer isolation film
70
P.
FIGS. 24
to
29
are sectional views for illustrating a method of manufacturing the semiconductor device
1
P. The method of manufacturing the semiconductor device
1
P is now described with reference to these drawings.
First, the element isolation films
51
P and
51
BP are formed in the surface
50
SP of the substrate
50
P for separating regions for forming the NMOSFETs
91
P and
92
P and the P-type layers
21
P and
22
P from each other.
Then, a resist film
81
P is arranged on the surface
50
SP while opening a region for forming the P well
12
P for ion-implanting a P-type impurity into the surface
50
SP through the resist film
81
P serving as a mask (see FIG.
24
). More specifically, boron is implanted, for example, under conditions of 300 keV to 1.5 MeV and 1×10
12
to 1×10
14
/cm
2
for forming a retrograde well, under implantation conditions of 80 keV to 160 keV and 1×10
12
to 5×10
13
/cm
2
for a channel-cut layer, and under implantation conditions of 15 keV to 70 keV and 3×10
12
to 5×10
13
/cm
2
for a threshold control layer, thereby forming the P well
12
P consisting of the retrograde well, channel-cut layer and threshold control layer.
Then, a resist film
82
P is arranged on the surface
50
SP while opening a region for forming the P well
11
P for ion-implanting a P-type impurity into the surface
50
SP through the resist film
82
P serving as a mask (see FIG.
25
). More specifically, boron is implanted, for example, under conditions of 200 keV to 500 keV and 5×10
12
to 1×10
14
/cm
2
for forming a retrograde well, under implantation conditions of 80 keV to 160 keV and 3×10
12
to 2×10
13
/cm
2
for a channel-cut layer, and under implantation conditions of 15 keV to 70 keV and 5×10
12
to 1×10
14
/cm
2
for a threshold control layer, thereby forming the P well
11
P consisting of the retrograde well, channel-cut layer and threshold control layer.
Thereafter N-type wells are formed in regions for forming NMOSFETs (not shown).
Thereafter films for the gate insulator films
63
P and the gate electrodes
62
P are formed and patterned into prescribed shapes, thereby forming the gate insulator films
63
P and the gate electrodes
62
P (see FIG.
26
). N-type extension layers
69
P are formed at the source/drain regions of the NMOSFETs, and P-type extension layers are formed at source/drain regions of the PMOSFETs (see FIG.
27
). While P-type extension layers
29
P are formed in regions for forming the P-type layers
21
P an
22
P, formation of such extension layers
29
P may be omitted. Thereafter an insulator film is formed to entirely cover the surface
50
SP and anisotropically etched thereby forming side-wall-spacers (hereinafter also referred to as “spacers”)
64
P.
Then, a resist film
83
P is arranged on the surface
50
SP while opening regions for forming the NMOSFETs
91
P and
92
P and regions for forming N-type layers for fixing the potentials of the N wells (not shown) for ion-implanting an N-type impurity into the surface
50
SP through the resist film
83
P serving as a mask (see FIG.
28
). For example, arsenic is implanted under conditions of 5 keV to 100 keV and 1×10
15
to 6×10
5
/cm
2
, thereby forming the source/drain regions
61
P of the NMOSFETs
91
P and
92
P and the aforementioned N-type layers.
Then, a resist film
84
P is arranged on the surface
50
SP while opening regions for forming the P-type layers
21
P and
22
P and the PMOSFETs for ion-implanting a P-type impurity into the surface
50
SP through the resist film
84
P serving as a mask (see FIG.
29
). For example, boron is implanted under conditions of 1 keV to 20 keV and 1×10
15
to 6×10
15
/cm
2
, thereby forming the P-type layers
21
P and
22
P and the source/drain regions of the PMOSFETs.
Then, the interlayer isolation film
70
P is formed entirely over the surface
50
S to cover the gate electrodes
62
P etc., and the contact holes
70
HP,
70
H
1
P and
70
H
2
P are formed in prescribed positions respectively. A conductive material such as a metal or polysilicon is deposited to cover the overall surface of the interlayer isolation film
70
P, thereby forming the contacts
31
P,
32
P and
65
P and the wires
40
P and
66
P. The semiconductor device
1
P shown in
FIG. 22
is completed through the

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