Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2001-01-04
2004-08-03
Clark, Sheila V. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S784000
Reexamination Certificate
active
06770963
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to the field of integrated circuit packages with multiple power supplies and more specifically to enabling greatly improved chip power bonding flexibility in systems integrating multiple complex functions to produce high functional density in compact electronic systems having high operational performance levels.
BACKGROUND OF THE INVENTION
An example of conventional integrated circuits and packages used in a conventional system with multiple power supplies (multi-power product) is an ordinary PC. Recent developments in highly compact, portable electronics may incorporate ICs in packages that have multiple functions requiring two or more different power supply leads or contacts for connection to electrically isolated or independent system power supplies. Industry today uses a mixed set of nomenclature designating IC packages with multiple and/or independent power supplies. Some of these are “multi-power level”, “multi-voltage level”. For the purposes of this discussion the term “multi-power chip” is used to designate a single IC chip/package having multiple functions that require multiple independent and/or electrically isolated power supply voltages (two or more, not counting ground return). These multiple voltages are provided by package electrical connections, i.e. power supply leads (conductive pads, pins or wires for mounting on a printed circuit board or substrate) for supplying different power supply voltages to internal functions separated or electrically isolated from each other.
Conventional IC packages preferred for such compact, portable electronic systems include those known as mini-BGA, micro-BGA, Flex-BGA, flip-chip-BGA, Film BGA, BCC, TFBGA and the like. Known examples are described by Schueller et al in U.S. Pat. No. 5,990,545, “Chip Scale Ball Grid Array for Integrated Circuit Package” the ″545 patent), by Eng et al in U.S. Pat. No. 5,952,611 “Flexible Pin Location Integrated Circuit Package” (the ″611 patent), and by Igarashi et al in U.S. Pat. No. 5,990,546 “Chip Scale Package Type of Semiconductor Device” (the ″546 patent), all incorporated herein by reference. The packages detailed in these patents described some of the known structural features for connecting external system power supply lines to the package external leads, and different organization, structure and formation of internal package insulating layers and conductive routing elements to provide a desirable arrangement of numerous isolated conductor paths to internal package bonding lands for subsequent convenient connection to selected chip bonding pads.
For example the ″546 patent shows chip electrode
11
(i.e. a chip bonding pad) coupled to an outer electrode
22
of the package through contact with a metallic bump
211
forming the inner end of inner electrode
21
. The inner electrode
21
is one end of a metal routing conductor
23
extending between insulating layers
24
and
25
and electrically connects outer electrode
22
to inner package electrode
21
.
Many techniques for forming arrangements of insulated routing conductors between inner package electrodes and outer package electrodes are known and are not part of the present invention. However, previously, conventional integrated circuit packages for systems attempting to integrate several or many disparate functions into a few packages or a single package present a number of chronic difficulties for the electronics industry. These difficulties are exaggerated especially in the area of attempting to integrate what previously have been separate functions into unitary or single modules. E.g. mobile phones containing one or more other functions: fax, messaging, microcomputer, personal digital assistants (PDAs) and the like.
To produce a single-chip system with multiple, disparate functions, such as a mobile phone combined for example with some computational capability, it may be necessary to combine RF power, analog processing, semiconductor RAM/ROM and CPU functions and perhaps flash memory. Each of these functions may work optimally at different power supply voltage levels, e.g., perhaps 10 volts for flash memory, 5 volts for the phone's RF transmitter and 3 volts for the RAM/ROM and 1.9 volts or less for the CPU.
Real world examples of these in particular include: single package memory subsystems with 3.3 v and 5 v power supply leads. Another single package solution is an entire PC having power supply voltages of 1.8 v (CPU), 3 v (memory), 5 v (logic) and 10 v (embedded flash memory).
The problems known in packaging multi-functional, multi-power level systems include power, ground, and I/O package pin count proliferation, the many-to-one relationship between chip power pads and multiple system power bus circuits (power bus nets), difficulty in reconciling chip bonding pad and package bonding area layouts with functional architecture, bonding ease, manufacturing throughput and cost, system board layout constraints, operating performance levels, signal transition speeds, lead inductance, I/O driver noise (ground bounce), signal cross-coupling, signal isolation, and others.
Power efficiency is a phrase sometimes used to indicate the degree to which the power requirements for the chip or die inside the package, are met by the available package pins (either the number of package pins or package lead count) or the topological placement of the internal package electrodes used as package electrode bonding areas (lands) relative to the chip bonding locations (pads). A typical example of some of these difficulties in the case of a multi-power IC chip with three different functions each requiring an independent power supply that is to be connected to a PC board system having 3 electrically isolated power supplies V
1
, V
2
and V
3
are shown with regard to FIG.
7
.
In
FIG. 7
, there is shown an example of preliminary bonding diagram
700
for multi-power IC chip
702
mounted in a prior art BGA package indicated by the arrow
700
. The BGA package
700
has 256 bonding lands arranged as 2 opposed rows and 2 opposed columns along the periphery of the package
700
and indicated by arrows
706
. 64 package bonding lands are arranged on each side of the package
700
and disposed to receive one end of a respective wire bond
744
connected at its other end to a respective chip bonding pad disposed on an adjacent chip edge.
The multi-power chip
702
has three separated or isolated power supply networks (nets)
710
,
720
and
730
. Four linear arrays of spaced apart chip bonding pads are arranged, one along each respective side of the nearly square chip
702
and indicated by arrows
740
pointing to two opposed rows and two opposed columns of chip bonding pad.
The chip
702
layout also includes chip signal traces (with associated bonding pads, not shown) connecting to a majority of the chip bonding pads
740
. The chip bonding pads comprise two major groups: chip signal bonding pads, e.g. pads
746
, and chip power bonding pads (CPpads). CPpads for the chip
702
are pads
711
-
715
,
721
-
724
, and
731
-
734
.
Each of the power nets
710
,
720
and
730
are connected to several particular chip power bonding pads selected from chip pads among the rows and columns
740
along each side of the chip
702
. Specifically, power net
710
is connected to particular chip power bonding pads
711
,
712
,
713
and
715
. Power net
720
is connected to particular chip power bonding pads
721
,
722
,
723
and
724
. Power net
730
is connected to particular chip power bonding pads
731
,
732
,
733
and
734
.
In this example, which is not a typical, the BGA package
700
was selected for a trial bonding diagram for mounting chip
702
because of size constraints imposed by the system for which the multi-power functions provided by chip
702
are intended. The board foot print for the
256
pin BGA package
700
is defined by package length
750
and package width
752
.
Although the package
700
meets the footprint requirement for the
Broadcom Corporation
Clark Sheila V.
Garlick Bruce
LandOfFree
Multi-power ring chip scale package for system level... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multi-power ring chip scale package for system level..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-power ring chip scale package for system level... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3354766