Semiconductor memory device switchable to twin memory cell...

Details Semiconductor memory device switchable to twin memory cell... Semiconductor memory device switchable to twin memory cell...

2002-11-19

2004-08-10

Mai, Son (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S222000

Reexamination Certificate

active

06775177

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to a semiconductor memory device capable of storing memory data corresponding to 1 bit of memory information represented as binary information, using two memory cells.
2. Description of the Background Art
In a DRAM (Dynamic Random Access Memory) as a representative example of semiconductor memory devices, generally, a memory cell storing 1 bit of data has one-transistor and one-capacitor structure. As the structure of the memory cell itself is simple, it has been used in various electronic equipment as most suitable for increasing degree of integration and capacity of semiconductor devices.
FIG. 13
is a circuit diagram showing a configuration of one of the memory cells arranged in a matrix of rows and columns in a memory cell array of a DRAM, in which each memory cell storing 1 bit of data has one-transistor and one-capacitor configuration (in the following, such a DRAM will be referred to as a single memory cell type DRAM).
Referring to
FIG. 13
, a memory cell
100
includes an N channel MOS transistor N
101
and a capacitor C
101
. N channel MOS transistor N
101
is connected to a bit line BL and capacitor C
101
, and has its gate connected to a word line WL. One end of capacitor C
101
different from the end connected to N channel MOS transistor N
101
, is connected to a cell plate
110
.
N channel MOS transistor N
101
is driven by a word line WL which is activated only at the time of data writing and data reading, and it is turned ON only at the time of data writing and data reading and otherwise kept OFF.
Capacitor C
101
stores binary information “1” and “0” dependent on whether charges are stored or not. When data is written to capacitor C
101
, bit line BL is precharged in advance to a power supply voltage Vcc or the ground voltage GND, corresponding to the write data. When word line WL is activated, N channel MOS transistor N
101
is turned on, and a voltage corresponding to the binary information “1” or “0” is applied from bit line BL through N channel MOS transistor N
101
to capacitor C
101
. Thus, capacitor C
101
is charged/discharged, and data is written.
When data is to be read, bit line BL is precharged in advance to a voltage Vcc/2. When word line WL is activated, N channel MOS transistor N
101
is turned on, and bit line BL and capacitor C
101
are conducted. Consequently, a slight change in voltage corresponding to the state of charge of capacitor C
101
appears on bit line BL, and the slight change in voltage is amplified by a sense amplifier, not shown, to the voltage Vcc or to the ground voltage GND. The voltage level of bit line BL corresponds to the state of the read data.
Here, in a memory cell of a DRAM, charges in capacitor C
101
that represent the stored data leak because of various factors, and are lost gradually. Specifically, the memory data is lost as time passes. Therefore, in the DRAM, before it becomes impossible to detect the change in voltage of bit line BL corresponding to the stored data in data reading, a refresh operation is executed, that is, the data is read once and written again.
Though the refresh operation is indispensable in the DRAM, it is disadvantageous in view of obtaining higher speed of operation. As a solution to this problem, a technique has been known in which a twin memory cell type memory configuration is adapted to allocate two memory cells for one bit of memory data, so that interval between refresh operations can be made longer and speed of access to the memory data can be increased.
FIG. 14
is a circuit diagram representing a configuration of memory cells arranged in a matrix of rows and columns in the memory cell array of a twin memory cell type DRAM.
Referring to
FIG. 14
, the memory cell in the DRAM has the twin memory cell type configuration in which two memory cells
100
A and
100
B are allocated for 1 bit of memory data, for storing the memory data and the inverted data thereof, respectively. Memory cell
100
A includes an N channel MOS transistor N
102
and a capacitor C
102
, and memory cell
100
B includes an N channel MOS transistor N
103
and a capacitor C
103
.
N channel MOS transistor N
102
is connected to one bit line BL of paired bit lines BL, /BL and to capacitor C
102
, and has its gate connected to word line WL
n
(n is an even number not smaller than 0). N channel MOS transistor N
102
is driven by word line WL
n
that is activated only at the time of data writing and data reading, and the transistor is turned ON only at the time of data writing and data reading and otherwise kept OFF.
N channel MOS transistor
103
is connected to the other bit line /BL of the paired bit lines BL, /BL and to capacitor C
103
, and has its gate connected to word line WL
n+1
. N channel MOS transistor N
103
is driven by word line WL
n+1
activated simultaneously with word line WL
n
, and the transistor is turned ON only at the time of data writing and data reading, and otherwise kept OFF.
Capacitors C
102
and C
103
store binary information “1” and “0”, dependent on whether charges are stored or not. Capacitor C
103
stores inverted data of the data stored in capacitor C
102
. Capacitor C
102
has one end connected to N channel MOS transistor N
102
and another end connected to a cell plate
110
. Capacitor C
103
has one end connected to N channel MOS transistor N
103
and another end connected to cell plate
110
.
When memory data of 1 bit is to be written to capacitors C
102
and C
103
, bit line BL is precharged to one of the power supply voltage Vcc and the ground voltage GND in correspondence with the write data, and bit line /BL is precharged to the other voltage, different from that of bit line BL. As word lines WL
n
and WL
n+1
are simultaneously activated, N channel MOS transistors N
102
and N
103
are simultaneously turned ON, a voltage corresponding to the memory data is applied from bit line BL through N channel MOS transistor N
102
to capacitor C
103
, and a voltage corresponding to the inverted data of the memory data is applied from bit line /BL through N channel MOS transistor N
103
to capacitor C
103
. Consequently, 1 bit of memory data is written to capacitors C
102
and C
103
.
When the memory data is to be read, the pair of bit lines BL and /BL are both precharged in advance to the voltage Vcc/2. When word lines WL
n
and WL
n+1
are simultaneously activated, N channel MOS transistors N
102
and N
103
are simultaneously turned ON, bit line BL is conducted to capacitor C
102
and bit line /BL is conducted to capacitor C
103
Thus, slight changes in voltages in opposite directions to each other appear on the pair of bit lines BL and /BL, and a sense amplifier, not shown, detects potential difference between the pair of bit lines BL and /BL and amplifies the difference to the voltage Vcc or to the ground voltage GND. The amplified voltage level corresponds to the state of the read memory data.
In the twin memory cell configuration, two memory cells are allocated to 1 bit of data. Therefore, the memory cell area is surely doubled as compared with the conventional memory cell. As the two memory cells store mutually inverted information, however, the amplitude of potential difference between the pair of bit lines BL and /BL is large, and therefore operation becomes stable and interval between refresh operations can advantageously be made longer.
Further, in the present twin memory cell type DRAM, the pair of bit lines BL and /BL are precharged to the voltage ½Vcc, as in a single memory cell type DRAM described above, at the time of data reading. Here, when the memory data is read to the pair of bit lines BL and /BL, the amplitude of voltage change on the bit lines corresponding to the memory data is double that of the single memory cell type DRAM described above, as the voltages on the pair of bit lines BL and /BL change in directions opposite to each other. Thus, the twin memory cell type DRAM additionally has an adva

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