Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-02-15
2004-08-10
Fourson, George (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S510000
Reexamination Certificate
active
06774439
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-039968, filed Feb. 17, 2000.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device using a fuse/anti-fuse system and a method of manufacturing the same.
In recent years, the semiconductor device is being made finer and finer to a high degree. In this connection, the element isolating region for isolating the element is formed mainly by a STI (Shallow Trench Isolation) method in place of the conventional LOCOS (Local Oxidation Of Silicon) method. It should be noted, however, that the film formed by the STI method has a very high surface flatness, with the result that, in the subsequent step of forming the gate electrode, it was necessary to employ the stepping process for forming an aligning mark.
FIGS. 28
to
33
are cross sectional views collectively showing the conventional process of manufacturing a semiconductor device. The conventional process of forming a semiconductor process will now be described with reference to
FIGS. 28
to
33
.
In the first step, a first concave portion
42
providing an element isolation region and a second concave portion
43
, which is used in the subsequent lithography process for forming an aligning mark, are formed in a silicon substrate
41
by a lithography technology and an RIE (Reactive Ion Etching) method, as shown in FIG.
28
.
In the next step, for example, a silicon oxide film
45
is formed on the entire surface so as to fill the first and second concave portions
42
and
43
with the silicon oxide film
45
, as shown in FIG.
29
. Then, the silicon oxide film
45
is removed by a CMP (Chemical Mechanical Polish) method until the surface of the silicon substrate
41
is exposed to the outside, thereby forming an element isolating region
46
of an STI structure in the first concave portion
42
.
After formation of the element isolating region
46
, a resist film
47
is formed on the entire surface, followed by patterning the resist film
47
by the lithography technology and the RIE method, as shown in FIG.
30
. Then, the silicon oxide film
45
within the second concave portion
43
is removed by the wet etching performed with the patterned resist film
47
used as a mask, thereby an aligning mark portion
53
is formed in the second concave portion
43
. Followed by removing the resist film
47
. In the following description, the step of removing the silicon oxide film
45
buried in the second concave portion
43
is called the stepping process.
In the next step, a gate insulating film
48
is formed on the entire surface, as shown in
FIG. 31
, followed by forming a polycrystalline silicon (polysilicon) film
49
on the gate insulating film
48
. Further a tungsten film
50
is formed on the polysilicon film
49
, and a silicon nitride film
51
is formed on the tungsten film
50
.
Then, the silicon nitride film
51
, the tungsten film
50
, the polysilicon film
49
and the gate insulating film
48
are selectively removed by the lithography technology and the RIE method, as shown in FIG.
32
. As a result, a gate electrode
52
is formed on a predetermined element region
46
a
. Incidentally, the gate insulating film of the gate electrode
52
is denoted by a reference numeral
48
a.
In the next step, a gate side wall
55
is formed on the side surface of the gate electrode
52
, and source-drain regions
56
are formed in surface regions of the silicon substrate
41
in contact with the edge portions of the gate insulating film
48
a
by the known technology, as shown in FIG.
33
. Then, an interlayer insulating film
57
is formed on the entire surface, followed by forming a contact plug
58
and an upper wiring layer
59
and subsequently forming another interlayer insulating film
60
on the entire surface.
Where the tungsten film
50
, etc. is used as a part of the gate electrode
52
as described above, it is difficult to read the difference in the film quality of the underlying layer by an optical method because the tungsten film
50
has a high reflectance. Therefore, if the stepping process for forming the aligning mark portion
53
, which is shown in
FIG. 30
, is omitted, it is impossible to read the aligning mark portion
53
by an optical method in the case of employing because the aligning mark portion
53
is no step, for example, the STI method that permits the formed film to have a high degree of surface flatness. It follows that the problem of the deviation in the alignment between the element isolating region
46
(or element region
46
a
) and the gate electrode
52
is rendered serious.
As described above, the lithography step and the etching step included in the stepping process are indispensable for avoiding the problem of the deviation in the alignment. However, since these steps are used solely for the stepping of the aligning mark portion
53
, it was desirable to omit these steps or to effectively utilize these steps.
On the other hand, in, for example, a DRAM (Dynamic Random Access Memory), the apparatus is equipped in many cases with a remedy circuit for substituting an auxiliary cell for the defective cell in order to improve the yield of the product. For the judgment of the cell that is to be renewed, it was customary to use a fuse of the type that the wiring made of mainly aluminum is fused away by a laser beam. On the other hand, proposed is an anti-fuse in which the judgment is performed by breaking the gate insulating film in a predetermined portion.
The anti-fuse is expected to produce various merits. For example, the anti-fuse is expected to decrease the area occupied within the chip and to permit replacing the final defective cell after sealing the package. Also, in the anti-fuse, a desired gate insulating film is broken to make the device conductive by applying a voltage higher than the breakdown voltage. Therefore, in general, the anti-fuse is connected to a high voltage generating circuit for breaking the gate insulating film and to a judging circuit for detecting whether the anti-fuse portion is broken or not. It follows that, in breaking the anti-fuse portion, the gate insulating film in the judging circuit portion also is damaged to some extent. Such being the situation, it was desirable to permit the anti-fuse portion to be broken with a reasonably low voltage while suppressing the damage done to the judging circuit and other portions as much as possible.
Also, in order to suppress the increase in the number of manufacturing steps, it is desirable to form the gate insulating film in the anti-fuse portion simultaneously with formation of the gate insulating film of the MOS transistor. However, it was difficult to form the gate insulating film of the anti-fuse portion having a low breakdown voltage simultaneously with formation of the gate insulating film included in the ordinary transistor and having a high reliability. Under the circumstances, it was difficult to put to the practical use the anti-fuse utilizing the gate insulating film formed for the transistor.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention, which has been achieved in an attempt to solve the above-noted problems, is to provide a semiconductor device that permits forming a gate insulating film having a desired breakdown voltage without increasing the number of manufacturing steps by applying the stepping process for forming an aligning mark to the formation of the anti-fuse and a method of manufacturing the particular semiconductor device.
According to a first aspect of the present invention, which permits achieving the object described above, there is provided a semiconductor device, comprising a concave portion formed in a semiconductor substrate, a first gate insulating film formed selectively on the semiconductor substrate, a second gate insulating film formed in at least the bottom surface of the concave portion, a first conductive film formed on the first gate insulating film, and a second conductive
Fukuzumi Yoshiaki
Kohyama Yusuke
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
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