Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2002-04-01
2004-06-22
Verbrugge, Kevin (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C710S240000
Reexamination Certificate
active
06754786
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for arbitrating a memory bus, access to which is requested by a plurality of data transfer circuits, and a memory control circuit for controlling a memory bus and a memory connected to the memory bus using the above method. In particular, the present invention relates to a method for arbitrating a memory bus connected to a plurality of data transfer circuits suitable for real-time processing such as moving picture processing, and a memory control circuit for performing the above method.
Some video apparatuses incorporates a memory device such as an SDRAM (Synchronous DRAM) that uses a DRAM (Dynamic Random Access Memory) as a core in order to store video data for video signal processing. This type of memory device is usually arranged so that both the data writing operation and the data reading operation are carried out using the same memory bus. The memory device, in which a write request and a read request are produced at the same time, should be equipped with an arbitrating device for arbitrating the memory bus in order to enable data transfer on a selective and time-shared basis in response to these requests. Further, even when a dual port memory is used which enables simultaneous execution of the writing operation and the reading operation, if more than two data transfer circuits request the access to the memory bus at the same time, it is required that the memory device be equipped with an arbitrating device for arbitrating the memory bus.
One of methods for arbitrating a memory bus when a plurality of data transfer circuits request the access to the memory bus is disclosed in, for example, a Japanese Patent No. 3,033,747 publication. A memory control circuit arranged with use of this prior art technique is shown in FIG.
12
.
In
FIG. 12
, a reference numeral
63
denotes a graphics data generation circuit for generating graphics data to be displayed on a display unit, a reference numeral
64
denotes a first SDRAM for storing the data generated by the graphics data generation circuit
63
, a reference numeral
65
denotes a second SDRAM for storing the data generated by the graphics data generation circuit
63
, a reference numeral
66
denotes a first display controller for transferring data stored in the first SDRAM
64
to a first display unit
71
(to be explained later), and a reference numeral
67
denotes a second display controller for transferring data stored in the second SDRAM
65
to a second display unit
72
(to be explained later). Further, in
FIG. 12
, a reference numeral
68
denotes a first memory bus which is used for transmitting and receiving data, addresses, commands and so on by the graphics data generation circuit
63
, the first SDRAM
64
and the first display controller
66
. Furthermore, in
FIG. 12
, a reference numeral
69
denotes a second memory bus which is used for transmitting and receiving data, addresses, commands and so on by the graphics data generation circuit
63
, the second SDRAM
65
and the second display controller
67
. Moreover, in
FIG. 12
, a reference numeral
70
denotes a bus arbiter which controls timing of data transfer executed by the graphics data generation circuit
63
, the first display controller
66
and the second display controller
67
in order to arbitrate the first memory bus
68
and the second memory bus
69
. Additionally, in
FIG. 12
, a reference numeral
71
denotes the first display unit which displays data transferred from the first display controller
66
, and a reference numeral
72
denotes the second display unit which displays data transferred from the second display controller
67
.
The prior art memory control circuit having the above-mentioned arrangements as shown in
FIG. 12
operates as follows.
The graphics data generation circuit
63
generates graphics data to be displayed on the first display unit
71
and the second display unit
72
. When completing generation of the graphics data to be displayed on the first display unit
71
, the graphics data generation circuit
63
transmits a first write request signal to the bus arbiter
70
to write the graphics data into the first SDRAM
64
. Further, the first display controller
66
incorporates a synchronization signal generation circuit for generating vertical and horizontal synchronization signals to drive the first display unit
71
. The first display controller
66
, whenever detecting a reference edge in the horizontal synchronization signal generated therein within an effective display period, transmits a first read request signal to the bus arbiter
70
to read out data stored in the first SDRAM
64
and to transfer it to the first display unit
71
.
Similarly, when completing generation of graphics data to be displayed on the second display unit
72
, the graphics data generation circuit
63
transmits a second write request signal to the bus arbiter
70
to write the graphics data into the second SDRAM
65
. The second display controller
67
incorporates a synchronization signal generation circuit for generating vertical and horizontal synchronization signals to drive the second display unit
72
. The second display controller
67
, whenever detecting a reference edge in the horizontal synchronization signal generated therein within an effective display period, transmits a second read request signal to the bus arbiter
70
to read out data stored in the second SDRAM
65
and to transfer it to the second display unit
72
. Generally, the period of the synchronization signal generated by the first display controller
66
is different from the period of the synchronization signal generated by the second display controller
67
.
The bus arbiter
70
receives first and second write request signals generated by the graphics data generation circuit
63
, a first read request signal generated by the first display controller
66
, and a second read request signal generated by the second display controller
67
. In response to four types of request signals received, the bus arbiter
70
generates four types of acknowledge signals for enabling execution of data transfer. More specifically, when data transfer is not executed in the first memory bus
68
during transmission of the first write request signal, the bus arbiter
70
transmits a first write acknowledge signal to the graphics data generation circuit
63
. When data transfer is not executed in the first memory bus
68
during transmission of the second write request signal, the bus arbiter
70
transmits a second write acknowledge signal to the first display controller
66
. When data transfer is not executed in the second memory bus
69
during transmission of the first read request signal, the bus arbiter
70
transmits a first acknowledge signal to the graphics data generation circuit
63
. When data transfer is not executed in the second memory bus
69
during transmission of the second read request signal, the bus arbiter
70
transmits a second read acknowledge signal to the second display controller
67
.
When receiving the first write acknowledge signal, the graphics data generation circuit
63
transfers data generated therein to the first SDRAM
64
via the first memory bus
68
. When completing the data transfer, the graphics data generation circuit
63
stops transmission of the first write request signal to the bus arbiter
70
. Further, when receiving the first read acknowledge signal, the first display controller
66
transfers data to be displayed for one horizontal period from the first SDRAM
64
to the first display controller
66
via the first memory bus
68
. When completing the data transfer, the first display controller
66
stops transmission of the first read request signal to the bus arbiter
70
. Further, the data transferred from the first SDRAM
64
to the first display controller
66
is transferred to the first display unit
71
together with the horizontal and vertical synchronization signals generated by the first display controller
66
.
Similarly, when receiving the second
Minami Kouji
Suzuki Yoshito
Mitsubishi Denki & Kabushiki Kaisha
Verbrugge Kevin
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