Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or...
Reexamination Certificate
2000-07-20
2004-08-17
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
C711S202000
Reexamination Certificate
active
06779072
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of computer busses, and more specifically to a method and apparatus for accessing memory-mapped registers that are distributed across a large integrated circuit.
BACKGROUND OF THE INVENTION
Computer systems and similar electronic systems and devices are being continually required to perform more operations at faster speeds with more reliability and less power consumption. The density or number of components or elements on a chip or circuit board are being driven up while packaging size and manufacturing costs are being driven down. This presents a challenge to designers to efficiently design systems and chips that optimally utilize the available real estate on a chip or printed circuit board. Additionally, components that need to communicate with one another are desirably located near one another to improve operational efficiency, reduce power consumption and reduce metallization for interconnectons and buses. For those components that because of other constraints must be placed at other locations, the challenge is to provide efficient interconnections for accessing these components.
Thus, there is a need for a method and apparatus for accessing different elements or components that are distributed across a large integrated circuit or distributed in different locations in a system.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for accessing memory-mapped registers that are distributed across a large integrated circuit.
One aspect of the present invention provides a method for accessing memory-mapped registers that are distributed across a first integrated circuit, the first integrated circuit including a plurality of logic subset modules, wherein each of the plurality of logic subset modules includes one or more memory-mapped registers. This method includes receiving a memory-mapped register access request into the first integrated circuit, serially transmitting, through each of the plurality of logic subset modules, a first plurality of data packets based on the memory-mapped register access request, wherein the first plurality of data packets includes an address specification for a memory-mapped register associated with a first one of the logic subset modules, and within the first logic subset module, accessing the memory-mapped register associated with the first logic subset module.
Another aspect of the present invention provides an MMR circuit for accessing memory-mapped registers that are distributed across a first integrated circuit chip, the first integrated circuit chip including a plurality of logic subset modules, the MMR circuit including a first receiver operable to receive a memory-mapped register access request into the first integrated circuit, an MMR control block within each one of the plurality of logic subset modules, and a ring controller having a serial bus connected through each of the plurality of MMR control blocks, the ring controller coupled to the first receiver and operable to generate a first plurality of data packets based on the memory-mapped register access request, wherein the first plurality of data packets includes an address specification for a memory-mapped register associated with a first one of the logic subset modules, wherein based on the address specification, the MMR control block within the first logic subset module, accesses the memory-mapped register associated with the first logic subset module.
Yet another aspect of the present invention provides a multiprocessor system having one of the MMR circuit embodiments described above. This system includes a plurality of integrated circuits including the first integrated circuit, one or more processors operably coupled to each one of the plurality of integrated circuits, a memory operably coupled to each one of the plurality of integrated circuits, and a network operably coupled to each one of the plurality of integrated circuits.
Still another aspect of the present invention provides computer system including one or more processor chips, an integrated circuit operably coupled to the one or more processor chips, the integrated circuit including a plurality of memory-mapped registers that are distributed across the integrated circuit, and means in the integrated circuit for accessing the memory-mapped registers.
REFERENCES:
patent: 4477713 (1984-10-01), Cook et al.
patent: 4514749 (1985-04-01), Shoji
patent: 4587445 (1986-05-01), Kanuma
patent: 4823184 (1989-04-01), Belmares-Sarabia et al.
patent: 4926066 (1990-05-01), Maini et al.
patent: 5295132 (1994-03-01), Hashimoto et al.
patent: 5315175 (1994-05-01), Langner
patent: 5394528 (1995-02-01), Kobayashi et al.
patent: 5416606 (1995-05-01), Katayama et al.
patent: 5481567 (1996-01-01), Betts et al.
patent: 5490252 (1996-02-01), Macera et al.
patent: 5506953 (1996-04-01), Dao
patent: 5521836 (1996-05-01), Hartong et al.
patent: 5535223 (1996-07-01), Horstmann et al.
patent: 5544203 (1996-08-01), Casasanta et al.
patent: 5555188 (1996-09-01), Chakradhar
patent: 5603056 (1997-02-01), Totani
patent: 5604450 (1997-02-01), Borkar et al.
patent: 5617537 (1997-04-01), Yamada et al.
patent: 5657346 (1997-08-01), Lordi et al.
patent: 5682512 (1997-10-01), Tetrick
patent: 5757658 (1998-05-01), Rodman et al.
patent: 5778429 (1998-07-01), Sukegawa et al.
patent: 5784706 (1998-07-01), Oberlin et al.
patent: 5787268 (1998-07-01), Sugiyama et al.
patent: 5793259 (1998-08-01), Chengson
patent: 5811997 (1998-09-01), Chengson et al.
patent: 5828833 (1998-10-01), Belville et al.
patent: 5844954 (1998-12-01), Casasanta et al.
patent: 5847592 (1998-12-01), Gleim et al.
patent: 5898729 (1999-04-01), Boezen et al.
patent: 4896272 (1999-06-01), Kurosawa
patent: 5910898 (1999-06-01), Johannsen
patent: 5915104 (1999-06-01), Miller
patent: 6005895 (1999-12-01), Perino et al.
patent: 6016553 (2000-01-01), Schneider et al.
patent: 6412056 (2002-06-01), Gharachorloo et al.
Gjessing et al.. Performance of the RamLink Memory Architecture. Proceedings HICSS'94, pp 154-162, 1994.*
Gjessing et al. RamLink: A High-Bandwidth Point-to-Point Memory Architecture. Proceedings CompCon 1992, pp 328-331, 1992.*
Gjessing et al. A RAM link for high speed. IEEE Spectrum, pp 52-53, 1992.*
Rao, A. Memory mapped registers. [Online] news://comp.arch.embedded, Apr. 27, 1996.*
Brewer, K. Re: Memory mapped registers, May 2, 1996.*
IEEE Std 1596.4-1996, IEEE standard for high-bandwidth memory interface based on Scalable Coherent Interface (SCI) signaling technology (RamLink), 1996.*
“Low Power Quad Differential Line Driver with Cut-Off”,National Semiconductor, F100K ECL 300 Series Databook and Design Guide, pp. 2-54—2-60,(1992).
“The SA27 library includes programmable delay elements Delaymuxo and Delaymuxn. How are these cells used?”,IBM Delaymuxn Book,pp. 1-6, (Feb. 1999).
Djordjevic, A.R., et al., “Time Domain Response of Multiconductor Transmission Lines”,Proceedings of the IEEE, 75 (6),743-64, (Jun. 1987).
Im, G., et al., “Bandwidth-Efficient Digital Transmission over Unshielded Twisted-Pair Wiring”IEEE Journal on Selected Areas in Communications, 13 (9),1643-1655, (Dec. 1995).
Mooney, R., et al., “A 900 Mb/s Bidirectional Signaling Scheme”,IEEE Journal of Solid-State Circuits, 30 (12),1538-1543, (Dec. 1995).
Takahashi, T., et al., “110GB/s Simulataneous Bi-Directional Transceiver Logic Synchronized with a System Clock”,IEEE International Solid-State Circuits Conference,176-177, (1999).
Anderson Michael L.
Fromm Eric C.
Sauder Mark F.
Choi Woo H.
Kim Matthew
Schwegman Lundberg Woessner & Kluth P.A.
Silicon Graphics Inc.
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