Minimally spaced MRAM structures

Details Minimally spaced MRAM structures Minimally spaced MRAM structures

2003-06-05

2004-06-15

Lebentritt, Michael (Department: 2824)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S257000, C438S258000, C438S259000

Reexamination Certificate

active

06750069

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates MRAM semiconductor structures and, more particularly, to a method of forming minimally spaced MRAM structures.
BACKGROUND OF THE INVENTION
Magnetic random access memories (MRAMs) employ magnetic multilayer films as storage elements. When in use, an MRAM cell stores information as digital bits, which in turn depend on the alternative states of magnetization of thin magnetic multilayer films forming each memory cell. As such, the MRAM cell has two stable magnetic configurations, high resistance representing a logic state 0 and low resistance representing a logic state 1, or vice versa.
A typical multilayer-film MRAM includes a number of bit or digit lines intersected by a number of word lines. At each intersection, a film of a magnetically coercive material is interposed between the corresponding bit line and digit line. Thus, this magnetic material and the multilayer films from the digit lines form a magnetic memory cell which stores a bit of information.
The basic memory element of an MRAM is a patterned structure of a multilayer material, which is typically composed of a stack of different materials, such as copper (Cu), tantalum (Ta), permalloy (NiFe) or aluminum oxide (Al
2
O
3
), among others. The stack may contain as many as ten different overlapping material layers and the layer sequence may repeat up to ten times. Fabrication of such stacks requires deposition of the thin magnetic materials layer by layer, according to a predefined order.
FIG. 1
shows an exemplary conventional MRAM structure including MRAM stacks
22
which have three respective associated bit or digit lines
18
. The digit lines
18
, typically formed of copper (Cu), are first formed in an insulating layer
16
formed over underlayers
14
of an integrated circuit (IC) substrate
10
. Underlayers
14
may include, for example, portions of integrated circuitry, such as CMOS circuitry. A pinned layer
20
, typically formed of ferromagnetic materials, is provided over each digit line
18
. A pinned layer is called “pinned” because its magnetization direction does not rotate in the presence of applied magnetic fields.
Conventional digit lines and pinned layers, such as the digit lines
18
and the pinned layers
20
of
FIG. 1
, are typically formed by a damascene process. Although damascene processes are preferred for copper interconnects, in the MRAM cell context the damascene process poses a drawback, in that there is an overlay of the pinned layer
20
with respect to the associated digit line
18
, which occurs primarily as a result of photoresist misalignment. On
FIG. 1
, this overlay is illustrated by an overlay distance D, on each side of the digit line
18
. Because of technical and processing limitations, conventional damascene processing is also unable to obtain long digit lines and their respective pinned layers.
Another drawback of using a conventional damascene process to produce the digit lines
18
of an MRAM is the inability of the process to achieve a minimal space or minimum critical dimension CD (
FIG. 1
) between two adjacent digit lines and, consequently, between two adjacent memory cells. Current values of the minimal space or critical dimension are in the range of 0.20 &mgr;m. However, with increased packing density of MRAM cells, the minimal space must decrease to values less than or equal to 0.1 &mgr;m, or even less than or equal to 0.05 &mgr;m, and current damascene processing does not afford these values with current 248 nm lithography.
Accordingly, there is a need for an improved method for fabricating MRAM structures, such as pinned layers and digit lines, which are minimally spaced from each other, as well as a method for decreasing the critical dimension between two adjacent MRAM structures formed on an integrated circuit substrate.
SUMMARY OF THE INVENTION
The present invention provides a method for forming minimally spaced MRAM structures, such as pinned layers and underlying digit lines, formed over various underlayers of an integrated circuit substrate. The present invention employs photolithography techniques to define masking patterns in an insulating layer formed over an integrated circuit substrate, by etching through a photolithography mask. The width of the masking patterns formed in the insulating layer is further reduced, for example by etching, to form reduced-width masking patterns, which are used to etch another insulating layer in which digit lines of MRAM structures are formed. The method of the present invention allows a further decrease in the critical dimension and tighter packing of MRAM structures subsequently formed.
These and other features and advantages of the invention will be more apparent from the following detailed description which is provided in connection with the accompanying drawings, which illustrate exemplary embodiments of the invention.


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