Computer graphics processing and selective visual display system – Computer graphics display memory system – Frame buffer
Reexamination Certificate
2002-03-28
2004-11-30
Tung, Kee M. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Frame buffer
C345S087000, C345S098000, C345S531000
Reexamination Certificate
active
06825845
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to virtual frame buffer controls, and more particularly to a system and method for cascading several display controllers associated with one liquid crystal display (LCD) panel.
2. Description of the Prior Art
The display memory for LCD displays in cell phones and Personal Data Assistance (PDA's) are beginning to be integrated into the display timing controller and source driver chips that drive the LCD panels. Integration of this display memory into these chips is problematic however, since the drivers can no longer be cascaded in a manner such as done in personal computer (PC) LCD solutions. In PC LCD displays, a number of different display resolutions can be supported with the timing controller and source drivers by simple cascading a different number of drivers for each different size display. In the PC LCD display, this technique of cascading source drivers was developed so that only one timing controller chip and one source driver chip was all a silicon company had to produce to support all the different sizes of display panels on the market. But in the PDA market it is desirable to integrate the source driver, timing controller, and display memory into just one chip. This technique is problematic since it requires cascading the memory whenever it is desired to cascade the source drivers; and when the memory is cascaded, the processor generating the display image must be able to map every displayable pixel to the proper controller/memory/source driver. This requirement has proven to be extremely problematic (i.e. ‘programming nightmare’), since even a simple operation such as drawing a line across a display image then requires a clipping window (implemented in software) for each controller/memory/source driver. This requirement for a software implemented clipping window associated with each controller/memory/source driver is extremely difficult to achieve due to the diverse types of buses that are used to interface the controller/memory/source driver devices to the processor. When data is sent to the controller/memory/source driver device, for example, there is no memory address associated with the data stream since the data has a predetermined destination. Further, the data transfer is generally implemented with a DMA controller. This means that if six controller/memory/source drivers are desired in the design, for example, the processor is required to cut the image being transferred into six pieces, and then program the DMA controller six different times to send the six different pieces to the six different controller/memory/source drivers.
SUMMARY OF THE INVENTION
The present invention is directed to a virtual frame buffer control system and method for cascading several display controllers on one LCD panel. The virtual frame buffer is composed of all the memory in all the controller/memory/source driver chips (in a tiled pattern) for the associated processor to read and write in. The control system also includes hardware clipping controls in each of the controller/memory/source driver chips. The virtual frame buffer and hardware clipping control placement substantially reduces programming problems associated with prior art solutions for cascading LCD controller/memory/source driver devices.
According to one embodiment, the associated processor reads and writes to the virtual memory; and each of the controller/memory/source driver devices will know when to capture its respective data off the data bus. This enables the processor to program the DMA controller such that the DMA controller will make only one transfer (the total uncut or uncropped image). Each controller/memory/source driver will monitor the data streaming across the bus and will know what portions of the two-dimensional image being transferred goes into it's own physical memory and what portions do not go into it's physical memory.
REFERENCES:
patent: 5546104 (1996-08-01), Kuga
patent: 6222564 (2001-04-01), Sturges
patent: 6282209 (2001-08-01), Kataoka et al.
patent: 6411302 (2002-06-01), Chiraz
patent: 6583771 (2003-06-01), Furuhashi et al.
patent: 2002/0008682 (2002-01-01), Park
patent: 2002/0070852 (2002-06-01), Trauner et al.
patent: 2003/0048275 (2003-03-01), Ciolac
patent: 2003/0074181 (2003-04-01), Gharavy
Brady III W. James
Kempler William B.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tung Kee M.
LandOfFree
Virtual frame buffer control system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Virtual frame buffer control system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Virtual frame buffer control system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3345774