Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing
Reexamination Certificate
2000-05-15
2004-02-17
Von Buhr, Maria N. (Department: 2125)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Product assembly or manufacturing
C700S110000, C714S742000, C702S081000
Reexamination Certificate
active
06694208
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a method of testing semiconductor devices, and more particularly, to an improved method of prioritizing failure modes to determine the cause of yield loss in a semiconductor manufacturing process.
BACKGROUND OF THE INVENTION
Semiconductor processing involves forming layers of materials on a semiconductor wafer and forming patterns on those layers to produce functional circuitry. A typical semiconductor wafer contains several dies (or chips) that are later packaged into individual integrated circuits. Errors may occur during the manufacturing process, rendering a percentage of the chips on a wafer to become defective. The yield rate is the percentage of chips that are functional relative to the total number of chips on a wafer. To improve yield rate, test structure, or test circuitry, is formed alongside the chips on the wafer to allow electrical tests to be conducted during and after the manufacturing process. Test signals are sent via probes into the test circuitry to measure certain parameters of a chip. These electrical tests may also measure parameters related to a group of chips that are adjacent to one another on the wafer. Usually when an equipment or process has errors, a number of parameters on a chip are affected. The characteristics of the chip as manifested by these parameters are called a “failure mode”. Different failure modes are linked to different kinds of errors that may occur in equipments or processes. Thus, a test that measures the parameters related to a particular failure mode can be used to determine whether a certain equipment or process is functioning properly.
Initially, a set of tests is conducted on a series of wafers, and a human operator determines whether the chips on the wafers show a particular failure mode. Test data obtained from a wafer that is determined to have a particular failure mode is stored in a database as the standard test data. When a subsequent wafer is processed, the new test data from the subsequently processed wafer is compared against the standard test data to determine whether the new wafer has a particular failure mode. If a new wafer shows a particular failure mode, then adjustments are made to the equipment or process that is related to that particular failure mode.
Typically, hundreds of wafers are processed in a semiconductor plant each day, each wafer contains hundreds of chips, and numerous electrical tests are performed on each of these chips. Thus, an enormous amount of data is generated from these tests. The task of comparing the new test data with the standard test data has been difficult and time consuming. Often several failure modes are detected on a wafer, or different wafers manifest different failure modes. The seriousness of the errors in the equipment or process that caused each failure mode may be different. Thus, it is desirable to know which failure mode contributed the most to yield loss. Traditionally, it has been difficult to automatically determine which parameter is most closely linked to the yield loss without human judgement.
The present invention is directed to a method of automatically determining the relationship between a failure mode and the yield loss, allowing a user to prioritize the failure modes for adjusting equipment or process and thereby effectively reducing yield loss.
SUMMARY OF THE INVENTION
A method for determining a failure mode with the greatest effect on yield loss in a semiconductor manufacturing process is disclosed. A predetermined number of wafers are processed, and each chip on each wafer is divided into a plurality of regions with each region having a plurality of cells. Electrical tests are performed on each cell, and a region is said to have a failure mode if one cell within the region has that failure mode. The yield loss contribution of a failure mode is determined by considering the yield loss from several wafers having that failure mode as the main failure mode. The yield loss contribution of a failure mode can also be determined by considering the percentage of defective chips on a wafer having that failure mode as the main failure mode. The failure mode with the highest yield loss contribution will have the greatest effect on yield loss.
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Cha Chia-Yen
Sheu Shiow-Hwan
Blakely , Sokoloff, Taylor & Zafman LLP
ProMos Technologies Inc.
Von Buhr Maria N.
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