Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2003-07-29
2004-08-10
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S660000, C438S663000
Reexamination Certificate
active
06774022
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to the fabrication of semiconductor devices and, more particularly, to a method of passivating an oxide surface subjected to a conductive material anneal, e.g., a titanium anneal.
BACKGROUND OF THE INVENTION
Various metalization, interconnect, and polycide formation processes are known and used in the fabrication of semiconductor devices. In the fabrication of many of such semiconductor devices, a conductive material such as titanium is used, for example, to form an ohmic contact to a silicon substrate. For example, in accordance with a conventional salicide or silicide fabrication process, titanium is often deposited on a semiconductor device structure which includes a silicon surface, e.g., contact area, and a silicon dioxide surface, e.g., field oxide surface. After forming a titanium layer on the silicon surface and silicon dioxide surface, the device structure may be subjected to a high temperature anneal, so as to form titanium silicide in the region where the titanium contacts the silicon surface and/or titanium nitride over portions of the structure.
In accordance with such a conventional fabrication approach, titanium oxide is likely to form at an interface between the titanium and silicon dioxide regions. During silicidation and/or salicidation processes, this interfacial titanium oxide formation can adversely affect the operational and reliability characteristics of the subject semiconductor device, such as by increasing contact resistance within the device and/or by encroaching into the active area of a circuit structure being formed. Undesirable titanium oxide formation may also adversely affect the thermal stability of the subject semiconductor device. The formation of interfacial titanium oxide during the fabrication of a titanium nitride local interconnect results in similar reliability and operational anomalies in the subject semiconductor device.
Further complicating known processes that utilize titanium in the fabrication of semiconductor device structures is the difficulty of removing titanium oxide within the device structure during conventional processing. By way of example, and in accordance with a conventional salicidation process, titanium oxide is generally not removed with use of traditional etching or cleaning techniques, during which undesired material such as titanium nitride or unreacted titanium is removed leaving titanium suicide as an ohmic contact to the silicon substrate.
SUMMARY OF THE INVENTION
There exists a keenly felt need in the semiconductor manufacturing industry for a method of reducing or substantially eliminating the likelihood of interfacial metal oxide formation, such as titanium oxide formation, at a titanium/silicon dioxide interface of a semiconductor device structure. There exists a further need for such a method that may be employed in silicidation, salicidation, and other fabrication processes, such as in the formation of interconnects. There exists yet a further need for such a method which may be easily integrated into existing fabrication processes without resort to additional processing components and without requiring significant modification to existing processing methods. The present invention fulfills these and other needs.
The present invention is directed to a method of preventing formation of titanium oxide within a semiconductor device structure during a high temperature treatment of the device structure. In particular, a method of forming a passivation layer in accordance with the present invention precludes formation of a metal oxide such as titanium oxide at a titanium/silicon dioxide interface of a semiconductor device structure.
A method according to the present invention for use in the fabrication of semiconductor devices includes forming an oxide region on a surface of a substrate. A layer of titanium is subsequently formed over a surface of at least the oxide region. Prior to forming the titanium layer, the substrate, including an oxide region, is exposed to a nitrogen containing atmosphere so as to inhibit formation of a titanium oxide layer on the oxide region surface during a subsequent thermal treatment.
In accordance with an embodiment of the present invention, a surface of the oxide region is exposed to a plasma containing nitrogen, such as a plasma comprising N
2
or NH
3
. A passivation layer, typically including Si
x
O
y
N
z
, is formed over the oxide surface, and titanium is subsequently deposited over the device structure. The device structure is subjected to a high temperature anneal or a rapid thermal) process in a nitrogen containing atmosphere or, alternatively, an atmosphere devoid of nitrogen.
In accordance with another embodiment, a method for use in the fabrication of a semiconductor device includes forming a layer of titanium on a surface including at least an oxide region. Prior to forming the titanium layer, the surface of the oxide region is treated so as to reduce diffusion of oxygen from the oxide region. The oxide region is treated by exposing the surface of the oxide region to a nitrogen containing plasma, such as a plasma comprising N
2
or NH
3
.
The above summary of the present invention is not intended to describe each embodiment or every implementation of the present invention. Advantages and attainments, together with a more complete understanding of the invention, will become apparent and appreciated by referring to the following detailed description and claims taken in conjunction with the accompanying drawings.
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Hu Yongjun Jeff
Li Li
Wang Zhongze
Lindsay, Jr. Walter L
Micro)n Technology, Inc.
Mueting Raasch & Gebhardt, P.A.
Niebling John F.
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