Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-11-05
2004-06-08
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S297000, C257S299000, C257S302000
Reexamination Certificate
active
06747303
ABSTRACT:
The invention relates to a charge detector semiconductor component in the form of a structure provided on a semiconductor material, which component comprises a non-volatile storage cell in the form of a MOS field effect transistor with a transistor gate and a MOS capacitor with a capacitor gate. The invention further relates to a system comprising a charge detector semiconductor component and a reference semiconductor component. The invention further relates to a wafer as well as to the use of a wafer with a number of charge detector semiconductor elements and/or systems. Finally, the invention relates to a method for the qualitative and quantitative measurement of charging of a wafer during processing of the wafer.
Wafer charging is a phenomenon that takes place continuously during the manufacture of semiconductor components, because many process steps take place in a plasma or are carried out by means of charged particles. In particular the thin gate oxides of MOS transistors in CMOS-type technologies, i.e. CMOS or BICMOS or similar technologies, can be destroyed by the charge collected on conductive surfaces, for example made of polycrystalline silicon or metal, during a process step and by the resulting tunnel current. This charging often is a cause of a low production yield.
It is attempted in product development to reduce the influence of the charging on the yield by means of so-called antenna rows.
During the process, test wafers are used, so-termed CHARM wafers (CHARging Monitors), in attempts to identify those process steps and pieces of equipment which cause particularly much charging and accordingly low yields.
Process monitoring by means of a CHARM wafer, however, is complicated and expensive, in particular because a production is to be interrupted for measuring one or several CHARM wafers.
JP-10-284726 describes a structure consisting of a p-channel and an n-channel MOS transistor and a method of measuring wafer charging in surroundings comprising a plasma. The structure requires a measurement before and after the plasma process step. This is only possible if the structure is contacted. This means that the monitoring of production goods having the structure can definitely be used for plasma steps at the end of a manufacturing process.
U.S. Pat. No. 5,959,309 describes a structure comprising an antenna, a diode string, a reverse-biased and a forward-biased transistor, and a storage capacitor for measuring wafer charging in surroundings comprising a plasma. A method in which the finished structure is placed in an instantaneous state in a plasma arrangement is also described therein. After completion of the plasma process, the end state is read out and compared with the original instantaneous state. A measure for charging in the step just carried out can be derived from the measured difference. An installation can be monitored by this method. The monitoring, however, cannot be carried out during the manufacture of useful material.
The methods of the two publications cited above have a number of disadvantages. Thus the expensive manufacturing installations are not operative during the monitoring of wafer charging. The production break causes considerable expense.
Furthermore, expensive test wafers such as those known, for example, as CHARM wafers, are required for monitoring.
Finally, the installation is checked at one particular moment only. The ongoing production, however, remains unchecked during this.
The structures described in JP-10-284726 and U.S. Pat. No. 5,959,309, furthermore, do not render possible a very accurate assessment of the charging. In particular, no analysis of any individual process step is possible.
Furthermore, the structures are not compatible with the CMOS manufacturing processes because they have no construction of the CMOS technology type and no circuits of the CMOS technology type, so that a number of process steps is necessary outside the CMOS technology standard. Thus it may be noted that the structure of JP 10-284726 is not compatible with the standard CMOS manufacturing method because it uses two polycrystalline silicon levels (
4
and
3
in FIG.
3
). The structure of U.S. Pat. No. 5,959,309 is not compatible with the standard CMOS manufacturing method because on the one hand it uses a high-quality capacitor (
46
in
FIGS. 4
a
and
4
b
) which would be manufactured with two superimposed polycrystalline silicon levels as a rule in a CMOS process. As a result, an additional polycrystalline silicon level becomes necessary again as compared with the standard CMOS process. On the other hand, the photodiode string (
43
in
FIG. 4
a
) requires the layers lying over the photodiode to be transparent. This, however, need not necessarily be the case in a standard CMOS process. Furthermore, a silicon semiconductor may not be capable of absorbing plasma radiation over the entire spectral range that occurs. An application of the structures described therein to production goods within the scope of a CMOS wafer processing is accordingly impossible.
A non-volatile storage cell is known from the publication “EEPROM-Struktur im CMOS-Technologie mit einer Polysiliciumebene” (EEPROM Structure in CMOS Technology with One Polycrystalline Silicon Level), Shaker Verlag, ISBN 3-8265-3289-9, Aachen 1998, and from WO 00/60672, which can be manufactured in a standard CMOS process. It is not suitable, however, for use as a monitor for wafer charging, i.e. as a wafer charging detector device.
It is an object of the present invention to provide a structure which is based on a non-volatile storage structure and which operates as a process control monitor (PCM) structure. It is a further object to indicate a use of the structure and a method whereby the charge can be measured which has arisen in a given location on a wafer during a process step, which structure was manufactured during the manufacture and/or processing of the wafer in a CMOS or BICMOS technology.
To achieve the object as regards the structure, the invention in a first embodiment is based on a charge detector semiconductor component in the form of a structure provided on a semiconductor material, which comprises a non-volatile storage cell in the form of
a MOS field effect transistor with a transistor gate, and advantageously also a source and a drain, and
a MOS capacitor with a capacitor gate, and advantageously also a source and a drain.
In such a charge detector semiconductor component, according to the invention, the following are provided:
an antenna which is in operational connection with the capacitor gate, wherein the capacitor gate is connected in a further operational connection to the transistor gate such that a charge arising on the antenna can be stored in the storage cell and can be retrieved upon demand, and wherein the structure is arranged in compatibility with the CMOS technology.
To achieve the object as regards the structure in a second embodiment, the invention offers the following:
a system comprising a charge detector semiconductor component and a reference semiconductor component, in the form of a structure provided on a semiconductor material, wherein the charge detector semiconductor component comprises a non-volatile detector storage cell in the form of
a first MOS field effect transistor with a detector transistor gate, and preferably also a source and a drain, and a first MOS capacitor with a detector capacitor gate, and preferably also a source and a drain, and comprises an antenna which is connected to the detector capacitor gate via
a first operational connection, wherein the detector capacitor gate is connected via a first operational connection, wherein the detector capacitor gate is connected to the detector transistor gate via a further first operational connection, and wherein
the reference semiconductor component comprises a non-volatile reference storage cell in the form of a second MOS field effect transistor with a reference transistor gate, and preferably also a source and a drain, and a second MOS capacitor with a reference capacitor gate, and preferably a
Koninklijke Philips Electronics , N.V.
Waxler Aaron
Wojciechowicz Edward
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