Method for forming planarized shallow trench isolation in an int

Details Method for forming planarized shallow trench isolation in an int Method for forming planarized shallow trench isolation in an int

1991-04-05

1992-07-14

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 72, 437 89, H01L 2176, H01L 21302

Patent

active

051302683

ABSTRACT:
A method for forming isolation structures in an integrated circuit, and the structures so formed, are disclosed. After definition of active regions of the surface is accomplished by provision of masking layers, recesses are etched into the exposed locations, to a depth on the order of the final thickness of the insulating isolation structure. Sidewall spacers of silicon dioxide, or another insulating amorphous material, are disposed along the sidewalls of the recesses, with silicon at the bottom of the recesses exposed. Selective epitaxial growth of silicon then forms a layer of silicon within the recesses, preferably to a thickness on the order of half of the depth of the recess. The epitaxial silicon is thermally oxidized, filling the recesses with thermal silicon dioxide, having a top surface which is substantially coplanar with the active regions of the surface. According to an alternative embodiment, the formation of the sidewall spacers may be done in such a manner that narrower recesses remain filled with the material of the sidewall spacers.

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