Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-02-20
2004-02-03
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S317000
Reexamination Certificate
active
06686622
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a floating gate EEPROM (Electrically Erasable and Programmable Read Only Memory) device. The invention more particularly relates to a semiconductor memory device and a manufacturing method of the same wherein a semiconductor substrate and a floating gate electrode are opposed to each other through an insulating film and the floating gate electrode covers a stepped portion provided at the semiconductor substrate.
The EEPROM device having a floating gate electrode is well known as an electrically programmable and erasable, nonvolatile memory.
In recent years, a so-called split gate type EEPROM device has been suggested. The memory is provided with a floating gate electrode on a side surface of the control gate electrode so that the device can operate at relatively low voltage.
Meanwhile, there has been a demand for a semiconductor device such as a transistor having an extra small size, a higher integration density, and higher reliability and exhibiting high performance. This also applies to the split gate type EEPROM device.
A conventional split gate type semiconductor memory device will be now described in conjunction with the accompanying drawings.
As shown in
FIG. 6A
, the semiconductor substrate
101
in the conventional semiconductor memory device has a first main surface
101
a
, a second main surface
101
b
positioned at a lower level than the first main surface
101
a
and a stepped portion
101
c
connecting these surfaces. A control gate electrode
104
is formed on the first main surface
101
a
through a first insulating film
103
serving as a gate insulating film.
There is a floating gate electrode
106
capacitively coupled through a second insulating film
105
on a side surface of the control gate electrode
104
on the side of the stepped portion
110
c
and opposed to the stepped portion
101
c
through the second insulating film
105
. The portion of the second insulating film
105
opposed to the control gate electrode
104
serves as a capacitive film, while the portion opposed to the channel region of the semiconductor substrate
101
serves as a tunnel film.
A source region
107
is formed by ion-implantation in a region included in the first main surface of the semiconductor substrate
101
. A drain region
108
is formed by ion-implantation in a region included in the second main surface.
However, as in
FIG. 6B
, an enlarged sectional view showing the vicinity of the stepped portion
101
c
, in the above conventional semiconductor memory device, the direction X of the first main surface and the side surface direction Y of the stepped portion
101
c
makes an obtuse dip angle &thgr; with respect to the upper side corner of the stepped portion
101
c
as the initial point. More specifically, the upper side corner of the stepped portion forms an acute angle and therefore the second insulating film (tunnel film)
105
is locally thinned at the corner. As a result, the second insulating film has a lowered breakdown voltage, which lowers the reliability of the memory device.
SUMMARY OF THE INVENTION
The present invention is directed to a solution to the above disadvantages associated with the conventional technique, and it is an object of the present invention to improve the reliability of a memory by preventing a tunnel film from being thinned by the presence of a stepped portion.
According to the present invention, in order to achieve the above object, a stepped region formed on a semiconductor substrate and covered by a floating gate electrode includes a plurality of stepped portions.
More specifically, a semiconductor memory device according to the present invention includes a control gate electrode formed on a first main surface of a semiconductor substrate through a first insulating film, and a floating gate electrode covering a stepped region which connects the first main surface of the semiconductor substrate and a second main surface positioned at a lower level than the first main surface through a second insulating film and having a side surface capacitively coupled with one side surface of the control gate electrode through a third insulating film. The stepped region has a first stepped portion connected with the first main surface and a second stepped portion connecting the first stepped portion and the second main surface.
In the semiconductor memory device according to the present invention, the height (depth) of each of the stepped portions is reduced, and therefore the dip angles at the corners of the stepped portions are acute. As a result, the second insulating film serving as a tunnel film covering the stepped region is not locally thinned at the corners of the stepped portions. Therefore, the breakdown voltage of the second insulating film is not lowered, and the device may have improved reliability.
Preferably, in the semiconductor memory device according to the present invention, the first and second stepped portions both have an acute dip angle, and the dip angle of the second stepped portion is larger than the dip angle of the first stepped portion.
In this case, the dip angle of the first stepped portion is preferably larger than 0° and substantially not larger than 50°.
A method of manufacturing a semiconductor memory device according to the present invention includes a first step of selectively forming a control gate electrode of a first conductive film on a first main surface of a semiconductor substrate through a first insulating film, a second step of selectively etching a region on one side of the control gate electrode at the semiconductor substrate, thereby forming a first stepped portion at an upper part of the semiconductor substrate, a third step of selectively etching a region on the opposite side of the control gate electrode with respect to the first stepped portion at the semiconductor substrate along the first stepped portion, thereby forming a second stepped portion connected to the first stepped portion and a second main surface connected to the second stepped portion at an upper part of the semiconductor substrate, a fourth step of forming a second insulating film to cover a side surface of the control gate electrode on the side of the first stepped portion, the first stepped portion, the second stepped portion, and the second main surface, a fifth step of forming a floating gate electrode of a sidewall-shaped second conductive film so that the electrode covers the side surface of the control gate electrode on the side of the first stepped portion, the first stepped portion, the second stepped portion and the second main surface through the second insulating film, and a sixth step of implanting an impurity to the semiconductor substrate using the control gate electrode and the floating gate electrode as masks, thereby forming a source region and a drain region on the first and second main surfaces, respectively.
By the method of manufacturing a semiconductor memory device according to the present invention, the second stepped portion connected to the first stepped portion and the second main surface connected to the second stepped portion are formed at an upper part of the semiconductor substrate. Therefore, if the second insulating film to be a tunnel film is subsequently formed to cover the stepped portions, the second insulating film is not locally thinned at the corners of the stepped portions. As a result, the breakdown voltage of the second insulating film is not lowered and the device may have improved reliability.
The method of manufacturing a semiconductor memory device according the present invention preferably further includes the step of implanting an impurity into a region on a side of the control gate electrode between the second step and the fifth step.
In the method of manufacturing a semiconductor memory device according the present invention, in the third step, the second stepped portion is preferably etched to a lower level than the first stepped portion.
Preferably, in the method of manufacturing a semiconductor memory device accordi
Noro Fumihiko
Ogura Seiki
Cao Phat X.
Doan Theresa T.
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
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